Comparison of FPGA and CPLD | Parameters of FPGA & CPLD | VLSI by Engineering Funda

Comparison of FPGA and CPLD is explained with the following timecodes:
0:00 - VLSI Lecture Series
0:29 - Comparison of FPGA and CPLD
0:40 - Block Diagram of FPGA and CPLD
2:54 - Full Form of FPGA and CPLD
3:07 - Architecture of FPGA and CPLD
4:02 - Blocks in Architecture of FPGA and CPLD
4:26 - Architecture tuning of FPGA and CPLD
6:47 - Architectural Memory of FPGA and CPLD
8:08 - Complexity of FPGA and CPLD
8:17 - Cost of FPGA and CPLD
8:24 - Time to ON of FPGA and CPLD
8:44 - Volatility of Program of FPGA and CPLD
9:06 - Power Consumption of FPGA and CPLD
9:19 - Timing Analysis of FPGA and CPLD
Following points are covered in this video:
0. Comparison of FPGA and CPLD
1. FPGA - Field Programmable Gate Array
2. CPLD - Complex Programmable Logic Design
3. Parameters of FPGA
4. Parameters of CPLD
Chapter-wise detailed Syllabus of the VLSI Course is as follows:
Chapter-1 Introduction to VLSI Design: • Introduction to VLSI D...
Evolution of Logic complexity, VLSI Design methodologies, Full Custom design and Semi Custom design, VLSI terminologies, Package Technology of IC, VLSI Design flow, Importance of CAD tools in VLSI, Comparison of FPGA, CPLD, PLC, DSP, Microcontroller and Microprocessor.
Chapter-2 CMOS Fabrication: • CMOS Fabrication
CMOS Fabrication process, Twin Tube CMOS Fabrication Process, Photolithography, Ion Implantation.
Chapter-3 MOS and MOSFET: • MOS and MOSFET
Two Terminal MOS structure, Flat band voltage, MOS under external bias, MOSFET, Threshold voltage of MOSFET, Gradual Channel Approximation of MOSFET, Channel Length Modulation of MOSFET, Substrate Bias Effect in MOSFET, MOSFET Capacitances, nMOS and pMOS, Examples on MOS, MOSFET, nMOS and pMOS.
Chapter-4 MOS Inverter: • MOS Inverter
nMOS Inverter, Noise Margin and Transfer characteristics of nMOS Inverter, Resistive Load Inverter, Depletion Load nMOS Inverter, CMOS Inverter, Voltage Transfer characteristics of CMOS Inverter, Parameters of CMOS Inverter, Examples on CMOS Inverter, Propagation delay of CMOS Inverter.
Chapter-5 CMOS circuits: • CMOS circuits
CMOS Circuits rules, CMOS NAND gate, CMOS NOR gate, Boolean function using CMOS, CMOS Multiplexer, CMOS SR Latch using NOR gates, CMOS SR Latch using NAND gates, CMOS D Latch, CMOS SR Flip Flop using NOR gates, CMOS JK Flip Flop using NOR gates, Stick Diagram, CMOS Transmission Gate, Multiplexer using Transmission gates, D Latch using Transmission gates, Boolean function implementation using transmission gates.
Chapter-6 Advanced CMOS: • Advanced CMOS
Dynamic CMOS, Cascading issues of dynamic CMOS, Comparison of static CMOS and Dynamic CMOS, Domino Logic CMOS, Charge sharing in Dynamic CMOS, Boolean function implementation using dynamic CMOS, NORA CMOS logic, Boolean function implementation using NORA CMOS, Voltage Bootstrapping, Latch Up in CMOS and Latch up prevention steps, FinFET Technology.
Chapter-7 Clock, Fault and Testing of VLSI: • Clock, Fault and Testi...
On Chip Clock Generation, Ring Oscillator, Clock Distribution, Faults in Integrated circuits, BIST - Bult In Self Test in Integrated circuit, Stuck at Fault.
Chapter-8 Verilog VHDL Programming: • Verilog VHDL Programming
Engineering Funda channel is all about Engineering and Technology. Here this video is a part of VLSI.
#FPGA #CPLD #VLSI #vlsidesign #EngineeringFunda

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[@habibullah7425]

sir, you are A LEGEND. hats off to you sir.
and your channel is criminally underrated, please do some SEO, so that your videos may pop up at the very top every time.

[@EngineeringFunda]

We are doing SEO of each and every videos. May be people are not connected as per my wish.

[@vardaansaproo1304]

I think the general structure of CPLD should contain the PLD blocks and the Switch Matrix.Can you clear this sir?

[@m.anitha6022]

Excellent Sir...i request you to do some videos on . Architecture: CPLD, FPGA and digital clock Design...thank you Sir

[@prabhatatha5543]

Sir you are explaining FPGA structure as cpld structure,and vice versa

[@Eurobunker]

@2:55 till the end: how did you manage the table rows keep flying in? This is an awesome way to do a comparison presentation. Thank You!

[@EngineeringFunda]

It is simple animation, make simple table with two colomn and 1 raw, and call it with one animation every once.

[@Eurobunker]

@@EngineeringFunda Thank You! Too bad, MS didn't think of a more capable table to animate without those "workarounds"...

[@muhammadhussain5906]

Thanks so much sir . MashAllah bohat acha samj aya

[@EngineeringFunda]

Your positive comments motivates me.
Teachers like me just wants positive comment from student.
Love from you guys means a lot to me.
My goal is to create largest community of engineers in entire globe. Please help me by sharing this playlist with your friends.

[@muhammadhussain5906]

@@EngineeringFunda ok sir in shaa Allah

[@mrpalevar]

I think the CLB block of FPGA is what you explained as CPLD block diagram. Pl verify

[@rkarthickraja5846]

Excellent teaching sir

[@EngineeringFunda]

Your positive comments motivates me, Thanks and welcome 🙏

[@jitendrameena236]

Sir where is yours previous video on this topic I didn't find it in your playlists

[@GautamKumar-eo7jj]

Fpga is not based on look up table, cpld is based on look up table, also complexity part so you have interchanged the points for fpga and cpld, watch video and think something is wrong.

[@mr.geetam]

CLB's are internal components of FPGA

[@friendshai7756]

Very clear

[@EngineeringFunda]

Love and happiness of students is my ultimate goal, God bless you 🙏, keep learning and keep progressing.

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Thanks a lot sir

[@EngineeringFunda]

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i appreciate your efforts

[@EngineeringFunda]

Your positive comments motivates me.
Teachers like me just wants positive comment from student.
Love from you guys means a lot to me.
My goal is to create largest community of engineers in entire globe. Please help me by sharing this playlist with your friends.

[@mohamedsajid1709]

Add more VLSI video

[@newtoninspired]

isn't it the CPLD which is LUT based?

[@akashverma7205]

good lecture

[@EngineeringFunda]

Your positive comments motivates me.
Teachers like me just wants positive comment from student.
Love from you guys means a lot to me.
My goal is to create largest community of engineers in entire globe. Please help me by sharing this playlist with your friends.

[@naveenyadav3489]

Woow...

[@EngineeringFunda]

Love and happiness of students is my ultimate goal, God bless you 🙏, keep learning and keep progressing.

[@mustafabootwala9334]

Sir what is array ??
There is lot of confusion in array.

[@EngineeringFunda]

Array means multiple elements

[@sudhanvagr]

PLC vs CPLD vs FPGA vs DSP vs Microcontroller vs Microprocessor comparison video if possible please.

[@EngineeringFunda]

I will look in to that matter

[@sudhanvagr]

@@EngineeringFunda thanks sir

[@EngineeringFunda]

Now it is available with my playlist of VLSI

[@sudhanvagr]

@@EngineeringFunda Thank you I'll look into it definately

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Thank you!!

[@EngineeringFunda]

Your positive comments motivates me, Thanks and welcome 🙏

[@capoeira347]

What language do you speack?

[@sa76893]

Gujrati

[@ouryoutubechannel3533]

What is the difference between clb and cpld

[@bunnytheweebster]

FPGA CLBs are complex and suited for high-density, complex logic. CPLD CLDs are simpler and better for low-density, basic logic.

[@somukrishcheri7829]

Full vlsi lecture upload sir plzz

[@EngineeringFunda]

By 2 months, it will be available with complete course

[@EngineeringFunda]

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TQ sir

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What is ur name sir ?

[@EngineeringFunda]

Hitesh

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Its more helpful if you add CC to the video's...

[@EngineeringFunda]

Noted

[@shaileshtalpada7809]

You made this video in hindi please

[@prabhatatha5543]

This video is wrong

[@sameersarrainodu1418]

cpld-complex programmable logic device😅😂

[@EngineeringFunda]

🙄

[@sameersarrainodu1418]

@@EngineeringFunda defination wrong bro