soo nice sir.... the explanation is superb ... I understand very much clear on this JTAG concept.... Thanks a lot...Please keep doing more videos on DFT concepts.. like ICG and latchup and negative and edge clock placement. Superb lecture sir... Thanks a lot once again
Hello, Firstly, nice video thanks. I have a question for the scan operation at 9:09. In your table you say that we don't care (X) what value has the *Mode* signal, and also you say that in this operation the system logic is isolated. But what will happen if we assign 1 to *Mode* signal? The *From system pin* it won't be connected with "To system logic" right? Thanks.
The value of Mode depends on what you wsnt to do. If you want to apply PI from the system pin, you set Mode=0. If you want to apply constant inpuy from FF, you set Mode =1.
Thanks a lot for the excellent lecture. The presentation goes straight to the nutshell of 1149.1 in a way that JTAG is no longer abstruse.
Only 20 comments?
But this was THE video which made me understand how JTAG really works inside the cells.
Your videos are extremely helpful for new test engineers like me. Thank you so much for sharing your knowledge in such a clear manner
Such a clear explanation sir.. thanks alot for creating VLSI testing videos.. very much helpful..
Thank you sir for your clear explanation. It is so informative. I can learn vlsi concepts easily from your videos.
soo nice sir.... the explanation is superb ... I understand very much clear on this JTAG concept.... Thanks a lot...Please keep doing more videos on DFT concepts.. like ICG and latchup and negative and edge clock placement. Superb lecture sir... Thanks a lot once again
Hey, you are my hero. I'm studying at the University of Applied Sciences Hochschule Augsburg and my prof is absolutely useless.
Watch out! there are eyes in dark place. Don't speak of anything bad about you prof
Great explanation sir, very useful for me to prepare for the final exam.
Hello,
Firstly, nice video thanks.
I have a question for the scan operation at 9:09.
In your table you say that we don't care (X) what value has the *Mode* signal, and also you say that in this operation the system logic is isolated. But what will happen if we assign 1 to *Mode* signal?
The *From system pin* it won't be connected with "To system logic" right?
Thanks.
The value of Mode depends on what you wsnt to do. If you want to apply PI from the system pin, you set Mode=0. If you want to apply constant inpuy from FF, you set Mode =1.
@@李建模-k8c Ohh ok, thanks
where is clock ir, clock dr, update clock coming?
TAP controller generates CLOCK IR, CLOCK DR, update DR and update IR. Instruction register generates CLOCK BR
Sorry, Instruction decoder generates CLOCK BR.
Hello,
Very nice video!!
I have a question : On which edge of TCK, ShiftDR and ShiftIR is generated??
This video audio is not working.
Thank you Sir.
🔥🔥
спасибо. эту часть нужно смотреть со старой версией ua-cam.com/video/XEN01h9qkC4/v-deo.html там более понятно