@@pyjamabrah To be honest, this is my Eureka moment. I always wanted to know why behind the C instead of just learning the syntax of it. This is the real Gold content I have been dreaming to find. Thank you for making it!
Was there any reason why you preferred the RISCV32i chip over an x86 chip in QEMU? I appreciate the lesson in cross compiling too, but was curious why. Thanks for making these. 10/10
Yes. The reason for RISC-V is that it is open, the documentation is available in plenty. There are few instruction in the ISA and it is way less complicated :)
crazy 🤯
Super amazing stuff 2.0❤🔥❤🔥
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@@pyjamabrah To be honest, this is my Eureka moment. I always wanted to know why behind the C instead of just learning the syntax of it. This is the real Gold content I have been dreaming to find. Thank you for making it!
@@pyjamabrah 100
Was there any reason why you preferred the RISCV32i chip over an x86 chip in QEMU? I appreciate the lesson in cross compiling too, but was curious why.
Thanks for making these. 10/10
Yes. The reason for RISC-V is that it is open, the documentation is available in plenty. There are few instruction in the ISA and it is way less complicated :)
@@pyjamabrah That makes perfect sense. Thank you so much!
Awesome content. Thank you so much
💘💝💖💗💓💞💕💟❣💔❤🔥💌