Logic Synthesis of RTL | Synopsys Design Compiler | Synopsys DC | dc_shell | DC Tutorial

This is the session-5 of RTL-to-GDSII flow series of video tutorial. In this session, we have demonstrated the synthesis flow of Synopsys Design compiler in the command line. We have started from the RTL code which has been checked for functionality and using the technology library and design constraints we have synthesized the RTL code into gate level netlist. During this logic synthesis process, our RTL code has been translated, optimized and mapped to the standard cells of the technology library. In this video, we have performed all the steps using command only, but a similar video using GUI mode only of Design compiler has been demonstrated in S-6 of this series.
In this RTL-to-GDSII flow of video series, there are total 10 sessions. We have covered all the stages of ASIC design using EDA tools demonstration and also the basic theories. Part-wise descriptions of the different session and the link of videos are as follow.
1. Session-1: Overview of RTL to GDSII flow | Basic terms in the flow
Video link: • RTL to GDSII flow | Ba...
2. Session-2: Flow in EDA tool's perspective | Different EDA tools | various files
Video link: • ASIC Flow and EDA tool...
3. Session-3: Functional verification of RTL | using Synopsys VCS | VCS demo
Video link: • RTL Design & Simulatio...
4. Session-4: Logic Synthesis flow | RTL to gate-level netlist | Design compiler
Video link: • Logic Synthesis flow |...
5. Session-5: Logic Synthesis | Design Compiler | Command-line | gate level netlist
Video link: • Logic Synthesis of RTL...
6. Session-6: Logic Synthesis | Design Compiler | GUI Mode| design_vision
Video link: • Logic Synthesis in Des...
7. Session-7: Logic Equivalence Check using Formality |S8| RTL-to-GDSII flow | Formality tutorial
Video link: • Logic Equivalence Chec...
8. Session-8: Physical Design Flow | PnR flow |RTL-to-GDSII flow | innovus flow
Video link: • Physical Design Flow |...
9. Session-9: Design Import | Physical Design |RTL-to-GDSII flow | innovus tools tutorial
Video link: • Design Import | Cadenc...
10.Session-10: Place and Route in Cadence Innovus | full PnR flow | Cadence Innovus demo
Video link: • Place and Route in Cad...
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[@aratidesai9146]

Thanks for all your videos.
All videos are very useful

[@TeamVLSI]

Hi Arati,
Glad you like them!

[@minhthien7073]

Thanks you. It is very helpful to the new like me.

[@prashanthreddy2163]

Your videos are really helpful. Could you also please make videos on learning TCL script

[@TeamVLSI]

Yes Prashanth, But it will take some time.

[@venoum0]

Thank you.Very informative videos

[@TeamVLSI]

You are welcome Debolina.
Keep supporting, Keep learning.

[@lavanyaekkandolla8512]

Hi, how to read the multiple files ( hierarchical design) in the dc shell? Is there any option to read the filelist?

[@mohannadasar6126]

You didn't associate the create_clock SDC command with the clk port [get_ports clk], is this why the timing report showing unconstraint path?

[@allachandrahas7951]

Thanks a lot for your efforts

[@TeamVLSI]

Thanks a lot @alla !!

[@Ganesh_Linga]

Tq so much of u sir... 👍

[@junqichen1790]

thank you sir，it is very useful. I want to know if there are relevant documents

[@dharamvirkumar558]

Hello sir, i am facing a problem when i am synthesizing a full adder in cadence genus..since it is a pure combinational circuit..do we still need to provide clock definitions in the .tcl file. Or how to synthesize a combinational circuit without .sdc file?

[@TeamVLSI]

Hi Dharamvir,
You can define a virtual clock.

[@pullepujaswanth5035]

sir, what about the zero wire load model that we use and can you differentiate different wire load models?

[@kailashprasad1137]

Can you tell me how to pass agument to the tcl file in dc_shell.
I m running dc_shell like this.
dc_shell-t -f /home/vlsi2018/BootLoader/syn.tcl

[@TeamVLSI]

You may open the dc shell first , then in tcl command window you can source the tcl file with argument.

[@naveenkabra5037]

please cover all these using VHDL codes
Thanks you

[@gopalag6916]

How to clear in unconnected error

[@thejanaidu4381]

Please cover all features of design complier sir.

[@TeamVLSI]

Hi Theja,
Thanks for the feedback.
Currently I am not getting chance to work on Design Compiler, But Yes , When I will get chance to work on it, I will work on your suggestion.

[@thejanaidu4381]

@@TeamVLSI any way ur explanations are really good. If you can. Please explain icc2 tool