Leveraging the RISC V Efficient Trace Standard - Iain Robertson, Senior Eng. Director, Tessent

Presenter - Iain Robertson
Senior Engineering Director - Hardware at Tessent, Siemens EDA.
Join Iain as he provides an expert insight into leveraging the RISC V Efficient Trace (E -Trace) Standard.
The Tessent Enhanced Trace Encoder is an exclusive software solution that helps organizations to manage the risk of adopting RISC-V architecture.
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ABOUT TESSENT SILICON LIFEYCYCLE SOLUTIONS
Tessent Silicon Lifecycle Solutions (formerly Mentor Graphics/UltraSoc) is a division of Siemens EDA (Siemens Digital Industries Software).
Tessent are widely recognized as the industry market leader in delivering design augmentation and linked applications that detect, mitigate and eliminate risks throughout the IC lifecycle. Tessent solutions help customers address their debug, test, yield, safety, security and optimization requirements for today’s most complex SoCs.
Tessent solutions fall into 2 key categories, Tessent Test and Tessent Embedded Analytics.
TESSENT TEST | Design for Test (DFT) and Yield Learning
DFT and yield learning products for logic, memory and mixed-signal devices.
The Tessent Test product suite provides comprehensive silicon test and yield learning applications that addresses the challenges of manufacturing test, debug, and yield ramp.
TESSENT EMBEDDED ANALYTICS | SoC Debug and Analytics
Tessent Embedded Analytics provides solutions for real-time debug and post-deployment analytics for RISC-V-based and other complex SoCs.
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LEARN MORE
Visit the Tessent website: eda.sw.siemens...
Email: [e-mail]
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