ZYNQ Training - Session 06 - AXI Stream Interface in Detail (HLS flow)

Web page for this lesson:
www.googoolia.c...
In this video we explore the AXI stream interface in more detail. We focus on creating modules with AXI stream interfaces using the Vivado HLS environment and the C Language. We go through the entire flow of synthesizing, simulating, and creating a packaged IP out of the design and then including the packaged ip into the project vivado project and connecting it to other components.
The material related to this course, and the files can be found at:
www.googoolia.com
www.green-elect...

[@emrahe468]

Everything is great with this video, with just a simple problem: copying and changing files and directories to create new projects, instead of using program interface (create new project)
Which may create some problems, if you are a newbie like me and not focusing %100 (such as assigning correct top function all the time manually)
Anyway the tutorials are still working on Vivado 2019.2, after 6 years :)

[@Caomusca]

I love how he starts the comments that describe a file by addressing his future self like "//Sadri, this is a file that does x y z.."

[@zr2089]

thanks very much. Really good job!

[@talebalashkar4397]

I am using vivado 2016 on windows 10.
I am not getting SystemC option in cosimulation and getting error to do both VHDL and Verilog simulation at time (42:00)
I seems there is problem in c++ compiler !
this is the message I am getting, any suggestion?
@I [SIM-47] Using XSIM for RTL simulation.
@I [SIM-14] Instrumenting C test bench ...
@W [SIM-75] Fifo port 'counter_output' has a default depth of 1. Insufficient depth may cause simulation mismatch or freeze. Please specify the depth in 'set_directive_interface' using the option '-depth'.
Build using "C:/Xilinx/Vivado_HLS/2016.1/msys/bin/g++.exe"
Compiling apatb_axi_stream_counter.cpp
Compiling axi_stream_counter.cpp_pre.cpp.tb.cpp
Compiling axi_stream_counter_test_bench.cpp_pre.cpp.tb.cpp
Compiling axi_stream_gpio.c_pre.c.tb.c
Generating cosim.tv.exe
@E [SIM-317] C++ compile error.
@E [SIM-321] EXE file generate failed.
@E [SIM-321] EXE file generate failed.
@E [SIM-331] Aborting co-simulation: C simulation failed, compilation errors.
@E [SIM-4] *** C/RTL co-simulation finished: FAIL ***

[@manuchaudhary7902]

In earlier videos ,you were using the bock diagram. Now are using the C code. Please Explain this. Also please show some demo of how your program runs on the ZYBO board.

[@dipeshpatil8717]

we are using C code to create a block of program.

[@jonreynolds7143]

Thanks for video. I am noticing that in my simulation of axi_stream_counter_range, after the reset goes high, the TREADY signal being output from the device is always set high. I would have expected it to only be high when the device is not busy counting (i.e. the same as yours). Apart from that, everything looks correct in my simulation waveforms. I am wondering if you know why this might be the case? Thanks.

[@kavinduvindikasomadasa352]

I think it's great if you can open it with vivado simulator... and by the way nice tutorial

[@andrelewis3942]

You mention there is a better way of accomplishing the GPIO example, could you explain what that is? Is it necessary to go through the memory map?

[@MohammadSSadri]

+Andre Lewis You mean AXI GPIO? Yes, that is a memory mapped device, but is very easy to use component. I think I have already explained this in my other videos.

[@josephliu4453]

thanks very much!

[@MA-kx8bg]

Thanks for nice tutorial.
I have question. What about tlast signal. if i use DMA to write data in DDR.How DMA will come to know end of stream as there is no tlast signal?

[@saranzeb7281]

can some one help me how create directory either we should create directory in HLS promt or window promt ? i think sir is using linux how to creat folder in windows?

[@deepakrishnamurthy2982]

hi,
how to restrict the ouput to only 4-bits?
Thanks in advance

[@MrPachaa94]

Hi,
I am looking for DVE but it seems to be licensed. Is there any low-cost or free tool to simulate IP cores?
Thanks in advance

[@MohammadSSadri]

use vivado itself.

[@MohammadSSadri]

also iverilog.wikia.com/wiki/GTKWAVE

[@strixneb]

I am using vivado hls 2014.1. I am unable to get to get the counter_output variable in the directives tab as demonstrated by you in the video at 17:28. What could be the reason?

[@samuelpereira8006]

I'm having the same problem with version 2016.2

[@reshmar1260]

Any one found solution?

[@eladiobarrioquerol5498]

i have the same problem D:

[@eladiobarrioquerol5498]

Ok, i find it in Xilinx forum:
yashkarundia
Newbie
‎11-24-2017 05:45 PM
You should check it in Project Settings - Synthesis - Top Function.

[@eladiobarrioquerol5498]

vivado only let me choose the correct one when i select browse

[@thaiquocthong4821]

bla bla bla 😭 40:08