Q. 6.17: Design a four‐bit binary synchronous counter with D flip‐flops || Complete design steps

[@carenyoussef6267]

Today is my birthday and u made it 10 times better.

[@spenceriannantuono9030]

Greatest of all time.

[@VigneshG-j8c]

super explanation

[@DIANEROSHANSAOB]

how do you do this in tinkercad?

[@purya8845]

Thank you so much, it was very helpful

[@veda6165]

do you have tutorials for wiritng a verilog program for this design?

[@jayantvijay1251]

how did you simplify D3 in last by abar b+ a b bar???????????

[@amnah3449]

Perfect explanation, thanks

[@marcelhusar7819]

Great explanation.

[@jakobnilsson679]

How would you go about this solution if you had to clock the counter manually, i. e. having one more signal (let's call it x)? Because in that case we can't solve it with Karnaugh, right? I have an assignment where I'm supposed to design a synchronous, manually clocked counter for 2-3-4-5-6-7-8, realised with D-flipflops, NAND-gates and inverters and am stuck at the state table.

[@byakuya_nati1225]

i guess you would have to use a 5 variable k-map

[@prathimareddy689]

Thankyou so much for the video.It helped me during my university practicals.

[@mayboyx]

Thank you so much!

[@aashnavaid6918]

thank you! it was helpful.

[@shanmugakamaleshm4254]

This problem is binary up or down?

[@fatemehmousavi5705]

Up

[@akhil9029]

@@fatemehmousavi5705 are you sure it is for up

[@fatemehmousavi5705]

@@akhil9029 If you mean that in this problem an up counter is designed, yes

[@akhil9029]

I have a question can we chat in what's app if you have time..?

[@fatemehmousavi5705]

@@akhil9029 no sorry

[@Ashatechdotcom]

Thanks abunch