Quick look at using GPT4 to code an ALU and test bench in Verilog.

Short, on-the-fly demo of using GPT-4 to generate an ALU in Verilog HDL, and a small Verilog test bench. Then we attempted to transform into structural Verilog, with a surprise construction of a full adder. Rounded out with generation of SystemVerilog Assertions (SVAs).
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