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Though it successfully generates a bit-stream there are timing error warnings due to excessive skew. How do you setup a timing constraint file for this example that gets rid of the warnings? -- Thanks!
Thank you so much sir. I have been trying it since so long. I could write clock divider code now, and it's working successfully too. Waiting for more such tutorials.
Thank you so much this is very helpful , I am using cyclone v DE10 standard board and its clock input is 50MHz this means that 25_000_000 cycles are on , correct ? and the code should be reg [14:0] count =0; reg clk_out always@(posedge clk_in) begin count
Nice tutorial sir, however i didn't get the point that is without assigning pins to clock and LED in the design file how vivado understood which pins to use for clk_in and LED. Can you please explain this.
Dear Dheeraj, @8:40 we use constraint files for basys 3 board and we use right most led on the board and system clock declared as output and input in the source file. Hope this helps.
@@ElectronicswithProfMughal Thank you sir, but I want to know just by declaring clk and led as input and output how vivado knows which pins to assign them. Sorry for my lame understanding.
I am using a Basys 3 board which has 16 leds, I can use any led I like. In the constraint file there are pin locations for every input and output. Those locations are also labelled on the board as well. In this video I chose the led which is on the very right. For every board, constraint file is given by the manufacturer. I suggest you watch this video: ua-cam.com/video/tOwMmBI_XNo/v-deo.html
sir i have one doubt here we haven't given initial value of clk_out . should'nt we give initial clk_out as '1' or '0' so that after it toogles. Kindly explain sir I m little confused in this point
Dear Kapil, you don’t necessarily have to do that because you’re defining positive edge of the clock here (meaning logic going from 0 to noon). So that means it waits for the positive edge and only then execute the commands.
Because one complete cycle is half off and half on. So if we divide 1M by half, we get 500_000. Means 500_000 cycles off, and 500_000 cycles it's on. That makes it a 1 Hz clock.
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This course is not found sir
please try this link - www.udemy.com/course/fpga-projects-using-verilog/@@khevanapurohit4440
Where do we find or generate xdc that is constraints file sir?
it will be in the project folder
Though it successfully generates a bit-stream there are timing error warnings due to excessive skew. How do you setup a timing constraint file for this example that gets rid of the warnings? -- Thanks!
Paste your warning here.
Thanks for the example!
You're welcome.
Hello but the led is blinking in the video is every 0.5 seconds not 1 seconds, can you clear the doubt.
Clock cycle is 1 second. Half of the time its off, half of the time its on.
Thank you so much sir. I have been trying it since so long. I could write clock divider code now, and it's working successfully too. Waiting for more such tutorials.
Thank you Dheeraj. Glad you find it useful :)
Sir could u please provide the test bench so that i can verify it in modelsim
If. Its not in the project folder, I don't have one.
Thank you so much this is very helpful , I am using cyclone v DE10 standard board and its clock input is 50MHz this means that 25_000_000 cycles are on , correct ?
and the code should be
reg [14:0] count =0;
reg clk_out
always@(posedge clk_in)
begin
count
The clk out part just simply helps mimic square wave, a digital signal. It is off for certain amount of time and it is on for certain amount of time.
Nice tutorial sir, however i didn't get the point that is without assigning pins to clock and LED in the design file how vivado understood which pins to use for clk_in and LED. Can you please explain this.
Dear Dheeraj, @8:40 we use constraint files for basys 3 board and we use right most led on the board and system clock declared as output and input in the source file. Hope this helps.
@@ElectronicswithProfMughal Thank you sir, but I want to know just by declaring clk and led as input and output how vivado knows which pins to assign them. Sorry for my lame understanding.
I am using a Basys 3 board which has 16 leds, I can use any led I like. In the constraint file there are pin locations for every input and output. Those locations are also labelled on the board as well. In this video I chose the led which is on the very right. For every board, constraint file is given by the manufacturer.
I suggest you watch this video:
ua-cam.com/video/tOwMmBI_XNo/v-deo.html
@@ElectronicswithProfMughal Got the point. Thank you sir.
sir i have one doubt here we haven't given initial value of clk_out . should'nt we give initial clk_out as '1' or '0' so that after it toogles. Kindly explain sir I m little confused in this point
Dear Kapil, you don’t necessarily have to do that because you’re defining positive edge of the clock here (meaning logic going from 0 to noon). So that means it waits for the positive edge and only then execute the commands.
I understand the logic does everything in parallel/concurrently.. yet this in this example the assignment to count seems like its sequential:
count
If you do that, it won't work. It will just simply stay solid. You should use the desire clock within the always@ block statement.
Sir why we have not use 100 million cycles ??
Because one complete cycle is half off and half on. So if we divide 1M by half, we get 500_000. Means 500_000 cycles off, and 500_000 cycles it's on. That makes it a 1 Hz clock.
its great thank u MR Mughal
sas wiko You’re welcome :)
Your student John Wei in ECE2029 just subscribed @ _ @
Thanks John :)