Fantastic practical capacitor analysis, thanks professor! I want to check that figure of merit for my past designs with mixed capacitors for some free context!
Thank u very much proffesor , i have never met with a guy who taught with such a simple technique and with simple examples too…your efforts to make the electronics designs better will be used by design engineers forever 😊
Yes thís is a real pointer, big enough for following everything perfect even on a little phonescreen! I had to start up my old phone to leave this comment but i am só glad with this, i must make an extra thank you! It is now.even better to follow because most of the surprising insights in these lessons you seem to speak without noticing that you Just filled in a hole in our understanding with only some words while circling aroumd it (so i only see now first time so clear!) Great, now even more! Thank you for this videolesson even more than
Another excellent video! I was going to ask if there was simulation support for the voltage dependence of type II ceramic capacitors, but when I googled it, another one of your videos that I missed showed up! Simulation of nonlinear effects of ceramic capacitors from June 10, 2017 Fantastic!
In practical EV inverters, I found that there are three main types of caps used. The stack of film capacitors of 10uF or 20uF. A couple of 2220 MLCC caps for each leg (usually 100nF and 10nF). And the last one is small capacitance (0.1 - 1uF, but high ripple current ones) metalized film caps that are directly put next to the leads of the SIC MOS or IBGT. Could you please explain the reasoning behind it? And how the impedance curve is designed in this case?
Thanks for the video Professor, Is there a reason for the video to specify ‘eMobility inverters’ in the title? I think that the concepts in it can be extrapolated to any kind of 3 phase inverter. Right?
Thanks for comment. I concentrated on a low voltage case which is associated with E-Mobility. For high voltage the considerations are somewhat different. E.g. film caps are attractive.
Hello Sam, top video as usual, i have a question tho, is it the same analysis done to design a dc link cap for dc-dc converters such as LLC tank converters?
Sorry, there is indeed a confusion here. Ls is the capacitor's inductance. The marked Ls in 8:25 is an inductor was put to prevent the voltage source from shorting the bus for AC and hence no ripple will penetrate the capacitors.
Hi Professor, How much does the ESL of the Electrolytic capacitor (or ceramic cap) affect the cap selection ? I have also noticed that the electrolytic capacitor datasheets do not provide ESL data or the SRF, they only provide tan delta. In simulations , I observe that the ESL of the cap has a really big impact on the ripple and also the VDS Spike during turn OFF of the FETs . Another request, would be great if you can make a video on the possible snubber circuits for inverters.
ESL is important, as you observed, generate spikes. Given for hybrid electrolytic . Parallel ceramic capacitors are recommended for simple aluminum caps. Look up my UA-cam channel for videos on snubbers.
Dear Professor, Thanks for such an informative video. However I have a doubt regarding Impedance calculations at 8:45 . Shouldn't it be Vripple=Ipk*Zc. Thanks in advance.
@@archie6586 Vripple=Ipk*Zc is incorrect. This expression is valid for a pure sinusoidal current while the ripple current includes higher harmonics characterized by sharp peaks. Vripple(rms) =Irms*Zc is a reasonable approximation considering that most of the energy is in the first harmonics.
I have a few questions about the simulation prof. To determine the value of the continuous phase current in the simulation, should the inductor use 1 µH or 1 mH? And what is the value of the capacitor?
Hi sir. Could you make a video on modelling phase-shifted inverters and how to implement control and compensation circuit with commertial ICs? All the ICs that I found was only for dc dc converter. thank you
@@sambenyaakov Hi proffesor. I have a question. After watching the professor's video many times, I still don't understand. With simulation professor parameters. Vbus 60V, I phase=100A, f=20kHz, how many electrolytic capacitors combined with how many caramic capacitors are needed to meet the rms ripple current parameters through the cap. Professor, can you tell me more about this issue?
@@ThanhThanh-zu3gu Once you decide what is the acceptable ripple voltage you select electrolytic caps to have a total ESR such that the expected ripple current time the ESR times the current will meet the voltage ripple requirement. The ceramic capacitors are then used to suppress the spikes due to the ESL of the electrolytic caps.
@@sambenyaakov Thank you professor for answering my question. I am designing an ESC for Drones. With ESC parameters I designed with parameters like Hobbywing's ESC (Platinum PRO V4 - 60A). Input Voltage 11,1V-22,2V, I phase rms=60A, f=20kHz.With this parameter, I calculated the current Icrms = 35A, but Hobbywing's ESC only uses 2 Rubycon series ZLJ (low ESR) 330uF capacitors with I ripple at 100kHz about 2A and ESR about 40mohm. Professor, can you help me answer this question? According to the professor's calculations, 17 capacitors in parallel are needed to meet the current Icrms=35A.
Thank you for this video for practical selection parameters of DC bus capacitor. 1)Will you please make a tutorial on thermal performance of DC link capacitor(Electrolytic, film and ceramic) and its life calculations(based on core temperature or ripple current) and its measurement methods. This will be very helpful for design engineers to calculate life of product. I have learnt so much from your tutorials.
Thkx for this video, I think that Z, its Imaginary part and ESR vary versus frequency, and at the switching frequency, Z is almost ESR, and ESR increases with skin effet over 500kHz, so 1. sizing C should pass by ESR first and we cannot link Vripple at switching frequency to Cw if we want exact calculation 2. the AC current spectrum should be analysed due to skin effect because of ESR increase. My question is how to calculate C value, il it is simple in PFC tanks to 100z component but here with only DC and Ripple at switching frequency I dont know how to determine C exactly. Best rergards
The total impedance of ceramic capacitors is larger than ESR all the way to the resonant frequency. This is why the capacitance is of concern. In electrolytic caps the concern is current.
@@sambenyaakov Thanks sir....in the DC link capacitor selection what is the role of modulation index and modulation type and does power factor play any role in battery powered system?Could you please explain.
The I is the actual ripple current of system which you can get by simulation as I have indicated, I think, in the video. The Vripple is a design constrain, depending on the max voltage of components and EMI constraints.
thank you professor, will you please mention the value of dc-link capacitance in the PSIM simulation. Also, is the phase current of 100 A rms, 100 Hz is drawn at unity power factor?
Cap value not important just big enough to capture most of the ripple current given the filter inductor. The pF as well the type of modulation will affect the value of the ripple current.
@@sambenyaakov @Sam Ben-Yaakov thank you very much...i simulated in simulink...initially the results did not match with yours as I considered controlled current sources...but later I changed them to R-L loads...so could match..and get proper FFT... congratulations and many many best wishes for your explanations.
Simulation of critical subcircuits always part of my design process. However one must consider the limitations of the circuit models you are using. In one portion of this video you stress using the frequency dependent ESR of the capacitor for the power dissipation and current sharing. However the ESR in the capacitor models I am aware of are fixed and not frequency dependent, so you would need to adjust that ESR in the model based on the dominant frequency component of the ripple current. Taking a stock capacitor model will probably not work. I have a video on measuring frequency dependent impedance with the Bode plot function of a modern oscilloscope and a current probe with many capacitor examples.
Thanks forthe comments. You seem to be unaware of the characteristics of ceramic capacitors (ESR frequency dependence). See: www.ee.bgu.ac.il/~pel/pdf-files/jour145.pdf ua-cam.com/video/yCK1hzgS_mU/v-deo.html ua-cam.com/video/vOsZD3rWCJM/v-deo.html ua-cam.com/video/2lfBvzhHsoc/v-deo.html
@@sambenyaakov I am very aware of the frequency dependence of ESR and voltage dependence of the capacitance. I was just expressing that the fixed lumped element models built in to circuit simulator do not easily model that behavior. One always need to understand the limitations of the models they use. If you look at the linked charts for the video I mentioned above you will see several examples of measured ESR vs. frequency. The minimum ESR I am measuring in the VNA videos is just a simple way to fit the capacitor impedance curve using simple fixed lumped element model available in circuit simulators and a quick way to compare capacitors in the lab. I fully understand that model (like most models) is not applicable to all situations. I have recently been experimenting with modeling the voltage dependence of ceramic capacitors in LTspice using capacitor model feature that allows you to insert an expression for the charge in which LT spice derives the capacitance from the voltage derivative. I have had limited success so far, but I still have had issues to work out. I have seen the videos you linked, they were excellent. Thank you for the link to your paper, I read it and am going to read a couple of your references. In your paper both the ESR (1) and EPR (4) are frequency dependent. I like the use of EPR in which the losses are voltage dependent since I would agree the dielectric losses are driven by the electric field. However frequency dependent device models for a transient simulation are not simple and may can cause convergence issues. It might be possible to implement frequency dependent models for harmonic balance simulation of a steady state fixed frequency condition. At the end of your video you talk about SPICE simulation. I would assume you use the frequency dependent ESR at the primary frequency in your capacitor models. However it would be nice to have a capacitor models with both the frequency and voltage dependence built-in.
@@Chris_Grossman Thanks for conversion. I think I understand now your points. For running the simulation I do not need a model. Since I assume a fixed frequency I just put an ideal cap R and L. For a deep analysis of capacitor simulations see www.ee.bgu.ac.il/~pel/pdf-files/jour143.pdf
Hi sir. Could you make a video on modelling phase-shifted inverters and how to implement control and compensation circuit with commertial ICs? because all the phase-shifted ics that I found was only for dc dc converters. Thank you.
One thing missing from the presentation- the working point of the system. In EV, and in fact, in most motion systems, it's a very rare condition when both current and voltage on the motor are near the rated values and the system works near full power. In reality, usually, it's either we are going fast with little effort or we are pushing hard to accelerate, while the speed is low. Therefore the real optimum is different. Also the prices of ceramic capacitors are higher than the electrolytes, unfortunately.
Well, 1. The capacitor ripple is caused by the phase current, that is the torque, not the voltage (hence not a direct function of the power). 2. I design systems to withstand the maximum stress, not the average
@@sambenyaakov when the voltage is 20%, the current seen by the bulk capacitors is 20%, isn't it? At least in RMS terms. Frankly I am not sure how important is the peak, but my guess is that if the heat of the electrolyte is a problem, peak doesn't matter much. As per maximum stress, i just mean that in certain systems marginal reliability is traded for cost, sometimes
@@lapserdak24 Again: the current ripple of the capacitors is a reflection of the phase current no matter what is the voltage. This video perhaps might help ua-cam.com/video/r_LmAsgfgrA/v-deo.html
@@sambenyaakov thank you very much for the video. This whole series would be helpful for me some 15 years ago :) and it's still interesting now. However I would like to argue that even though the bulk capacitor current reflects the phase current, it is related to voltage as well. Its pretty obvious actually - neglect the losses, if motor voltage is 20% of the bus voltage then the bridge input (sitting on the full bus voltage) sees 20% of the current. Same amplitude, low duty cycle. Therefore the bulk capacitors at best see the 20%, and in fact less- part of the current comes from the battery. So if we have a system where the battery is 60V and the motor never goes higher than 40V, the worst case will simply never occur.
@@sambenyaakov I mean to say "what if other than 40kHz component also present in the capacitor current with significant magnitude"? Eg: if there is an rectifier instead of battery, with very less cable inductance..
@@maheshkumarnandigama2756 If one is, say, up to 30 percent of the other it can be neglected. Otherwise is is best examined by simulation in lieu of lengthy calculations.
Do you have a video covering AC voltage across class 1 MLCC capacitors? I bought some from LCSC rated for 630VDC at 15nF 1210 package size. They have pretty high Q factor, I think the datasheet specified minimum of 600? Pictures found here: imgur.com/gallery/8gYl5Qr I put them to use in a DRSSTC tesla coil (a series resonant LC converter) and found that I could get some good performance from them, they did tend to crack, explode, and fail short-circuit, usually melting like glass due to the high voltage DC arc.
Check the dU/dt of your circuit and chose the capacitors accordingly. If their max dU/dt is not specified, don‘t use them. Also they have to stand the average current without getting to hot (short high current pulses of some us no problem mostly) There is a reason, most smd capacitors do not have any current spec: They suck at it. There are some RF COQ types on the market to meet the demand, but they are really expensive. Used in space, oil drills and warfare.
![Lp. Сердце Вселенной #60 РОЖДЕНИЕ ЛОЛОЛОШКИ [Финал] • Майнкрафт](http://i.ytimg.com/vi/YoR0pAV9FVQ/mqdefault.jpg)
Fantastic practical capacitor analysis, thanks professor! I want to check that figure of merit for my past designs with mixed capacitors for some free context!
👍
Thank u very much proffesor , i have never met with a guy who taught with such a simple technique and with simple examples too…your efforts to make the electronics designs better will be used by design engineers forever 😊
Thanks. Comments like yours keep me going.
I'm finding a very interesting presentation, today I learnt something new and very helpful for my ESC project I'm working on. Thanks again, professor!
Thanks for comment
It seems Professor Sam exactly knows what I am looking for!
👍
Very informative sir...... God bless u.... I wish I could've got a teacher like u in my graduation course
Thanks for kind words
I can not thank you enough. I was looking for this for two months.
😊🙏
@@sambenyaakov Would you please explain, how did you get 1.7A for 180 uf capacitor at time @22.01 minutes? Thanks in advance.
Yes thís is a real pointer, big enough for following everything perfect even on a little phonescreen! I had to start up my old phone to leave this comment but i am só glad with this, i must make an extra thank you! It is now.even better to follow because most of the surprising insights in these lessons you seem to speak without noticing that you Just filled in a hole in our understanding with only some words while circling aroumd it (so i only see now first time so clear!) Great, now even more!
Thank you for this videolesson even more than
👍
Another excellent video! I was going to ask if there was simulation support for the voltage dependence of type II ceramic capacitors, but when I googled it, another one of your videos that I missed showed up!
Simulation of nonlinear effects of ceramic capacitors from June 10, 2017
Fantastic!
😊
In practical EV inverters, I found that there are three main types of caps used. The stack of film capacitors of 10uF or 20uF. A couple of 2220 MLCC caps for each leg (usually 100nF and 10nF). And the last one is small capacitance (0.1 - 1uF, but high ripple current ones) metalized film caps that are directly put next to the leads of the SIC MOS or IBGT. Could you please explain the reasoning behind it? And how the impedance curve is designed in this case?
You are talking about a high voltage system. In this case, as mentioned in video, film caps are effective.
Amazing video. Thank you professor.
Thanks
Very useful and elaborate presentation Dr. Yakoov
Thanks Asif
Thank you very much, this video give me a lot of inspiration about bus capacitor design.
👍🙏
Thank you so much for your great explanation s
Thanks
Thanks for the video Professor, Is there a reason for the video to specify ‘eMobility inverters’ in the title? I think that the concepts in it can be extrapolated to any kind of 3 phase inverter. Right?
Thanks for comment. I concentrated on a low voltage case which is associated with E-Mobility. For high voltage the considerations are somewhat different. E.g. film caps are attractive.
Hello Sam, top video as usual, i have a question tho, is it the same analysis done to design a dc link cap for dc-dc converters such as LLC tank converters?
Yes indeed. Thanks
Dear professor, nice video. I have one doubts 8:25 you taken Ls as 1uH. But in simulation, you taken Ls as 1mH. Can i know the reason behind in this?
Sorry, there is indeed a confusion here. Ls is the capacitor's inductance. The marked Ls in 8:25 is an inductor was put to prevent the voltage source from shorting the bus for AC and hence no ripple will penetrate the capacitors.
Hi Professor,
How much does the ESL of the Electrolytic capacitor (or ceramic cap) affect the cap selection ?
I have also noticed that the electrolytic capacitor datasheets do not provide ESL data or the SRF, they only provide tan delta.
In simulations , I observe that the ESL of the cap has a really big impact on the ripple and also the VDS Spike during turn OFF of the FETs .
Another request, would be great if you can make a video on the possible snubber circuits for inverters.
ESL is important, as you observed, generate spikes. Given for hybrid electrolytic . Parallel ceramic capacitors are recommended for simple aluminum caps. Look up my UA-cam channel for videos on snubbers.
So good
Thank you professor 🙏
Thanks for note.
Dear Professor, Thanks for such an informative video. However I have a doubt regarding Impedance calculations at 8:45 . Shouldn't it be Vripple=Ipk*Zc. Thanks in advance.
What do you mean? missing *?
@@sambenyaakov . Professor in the slide it is mentioned as Vripple=Irms*Zc . Shouldn't it be peak current i.e. Vripple=Ipk*Zc
@@archie6586 Vripple=Ipk*Zc is incorrect. This expression is valid for a pure sinusoidal current while the ripple current includes higher harmonics characterized by sharp peaks. Vripple(rms) =Irms*Zc is a reasonable approximation considering that most of the energy is in the first harmonics.
Which software you are using for simulation?
LTspice ans PSIM
I have a few questions about the simulation prof. To determine the value of the continuous phase current in the simulation, should the inductor use 1 µH or 1 mH? And what is the value of the capacitor?
Sorry, not sure I followed your question.
@@sambenyaakov If I want to get continuous phase current 177A, what parameters need to be configured in simulation?
@@indraq-e4s What is the motor model you use in the simulation?
@@sambenyaakov May I request your PSIM simulation file, Professor? I would like to compare it with my simulation results.
Handy video for power electronics engineers.
Thanks
Thank you! Professor.
Thanks
Thank you professor Ben-Yaakov, sir
Thanks
Hi sir.
Could you make a video on modelling phase-shifted inverters and how to implement control and compensation circuit with commertial ICs? All the ICs that I found was only for dc dc converter.
thank you
Very interesting presentation, Thank u very much proffesor.
Thanks
@@sambenyaakov Hi proffesor. I have a question. After watching the professor's video many times, I still don't understand. With simulation professor parameters. Vbus 60V, I phase=100A, f=20kHz, how many electrolytic capacitors combined with how many caramic capacitors are needed to meet the rms ripple current parameters through the cap. Professor, can you tell me more about this issue?
@@ThanhThanh-zu3gu Once you decide what is the acceptable ripple voltage you select electrolytic caps to have a total ESR such that the expected ripple current time the ESR times the current will meet the voltage ripple requirement. The ceramic capacitors are then used to suppress the spikes due to the ESL of the electrolytic caps.
@@sambenyaakov Thank you professor for answering my question. I am designing an ESC for Drones. With ESC parameters I designed with parameters like Hobbywing's ESC (Platinum PRO V4 - 60A). Input Voltage 11,1V-22,2V, I phase rms=60A, f=20kHz.With this parameter, I calculated the current Icrms = 35A, but Hobbywing's ESC only uses 2 Rubycon series ZLJ (low ESR) 330uF capacitors with I ripple at 100kHz about 2A and ESR about 40mohm. Professor, can you help me answer this question? According to the professor's calculations, 17 capacitors in parallel are needed to meet the current Icrms=35A.
@@ThanhThanh-zu3gu Total ESR is 2.3. Looks reasonable. I think you can find 150uF with 1.5 Amp - see if it is better.
Thank you for this video for practical selection parameters of DC bus capacitor.
1)Will you please make a tutorial on thermal performance of DC link capacitor(Electrolytic, film and ceramic) and its life calculations(based on core temperature or ripple current) and its measurement methods.
This will be very helpful for design engineers to calculate life of product.
I have learnt so much from your tutorials.
Thanks for comment. As for suggestion, not simple, will try.
Yes sir please ..it will be very much helpful for design engineer as its very hard to get intuitive explanation like this
Thkx for this video, I think that Z, its Imaginary part and ESR vary versus frequency, and at the switching frequency, Z is almost ESR, and ESR increases with skin effet over 500kHz, so 1. sizing C should pass by ESR first and we cannot link Vripple at switching frequency to Cw if we want exact calculation 2. the AC current spectrum should be analysed due to skin effect because of ESR increase. My question is how to calculate C value, il it is simple in PFC tanks to 100z component but here with only DC and Ripple at switching frequency I dont know how to determine C exactly. Best rergards
The total impedance of ceramic capacitors is larger than ESR all the way to the resonant frequency. This is why the capacitance is of concern. In electrolytic caps the concern is current.
How did u define the initial capacitor and inductor value in the beginning.
To which minute in video are you referring to?
Thanks for the video
Thanks
Can we do same analysis using I=C* dv/dt...I am really excited to see how can we do the same analysis using above equation or can you give some hints
I do not think this is a good path to go. Perhaps using first harmonics then Cw= Irms/Vrms
@@sambenyaakov Thanks sir....in the DC link capacitor selection what is the role of modulation index and modulation type and does power factor play any role in battery powered system?Could you please explain.
Thank you! Very Interesting content!
Thanks
How do you choose the Vripple, and the Irms for a VSC?
The I is the actual ripple current of system which you can get by simulation as I have indicated, I think, in the video. The Vripple is a design constrain, depending on the max voltage of components and EMI constraints.
Hi professor, how about Class 1 ceramic capacitor that don't suffer DC bias degradation on capacitance?
They are excellent but limited to up to 0.1uF
thank you professor, will you please mention the value of dc-link capacitance in the PSIM simulation. Also, is the phase current of 100 A rms, 100 Hz is drawn at unity power factor?
Cap value not important just big enough to capture most of the ripple current given the filter inductor. The pF as well the type of modulation will affect the value of the ripple current.
@@sambenyaakov @Sam Ben-Yaakov thank you very much...i simulated in simulink...initially the results did not match with yours as I considered controlled current sources...but later I changed them to R-L loads...so could match..and get proper FFT... congratulations and many many best wishes for your explanations.
@@ramkrishnahari3838 May I ask for the Simulink simulation file?
Simulation of critical subcircuits always part of my design process. However one must consider the limitations of the circuit models you are using.
In one portion of this video you stress using the frequency dependent ESR of the capacitor for the power dissipation and current sharing. However the ESR in the capacitor models I am aware of are fixed and not frequency dependent, so you would need to adjust that ESR in the model based on the dominant frequency component of the ripple current. Taking a stock capacitor model will probably not work.
I have a video on measuring frequency dependent impedance with the Bode plot function of a modern oscilloscope and a current probe with many capacitor examples.
Thanks forthe comments. You seem to be unaware of the characteristics of ceramic capacitors (ESR frequency dependence). See:
www.ee.bgu.ac.il/~pel/pdf-files/jour145.pdf
ua-cam.com/video/yCK1hzgS_mU/v-deo.html
ua-cam.com/video/vOsZD3rWCJM/v-deo.html
ua-cam.com/video/2lfBvzhHsoc/v-deo.html
@@sambenyaakov I am very aware of the frequency dependence of ESR and voltage dependence of the capacitance. I was just expressing that the fixed lumped element models built in to circuit simulator do not easily model that behavior. One always need to understand the limitations of the models they use.
If you look at the linked charts for the video I mentioned above you will see several examples of measured ESR vs. frequency. The minimum ESR I am measuring in the VNA videos is just a simple way to fit the capacitor impedance curve using simple fixed lumped element model available in circuit simulators and a quick way to compare capacitors in the lab. I fully understand that model (like most models) is not applicable to all situations.
I have recently been experimenting with modeling the voltage dependence of ceramic capacitors in LTspice using capacitor model feature that allows you to insert an expression for the charge in which LT spice derives the capacitance from the voltage derivative. I have had limited success so far, but I still have had issues to work out.
I have seen the videos you linked, they were excellent. Thank you for the link to your paper, I read it and am going to read a couple of your references.
In your paper both the ESR (1) and EPR (4) are frequency dependent. I like the use of EPR in which the losses are voltage dependent since I would agree the dielectric losses are driven by the electric field. However frequency dependent device models for a transient simulation are not simple and may can cause convergence issues. It might be possible to implement frequency dependent models for harmonic balance simulation of a steady state fixed frequency condition.
At the end of your video you talk about SPICE simulation. I would assume you use the frequency dependent ESR at the primary frequency in your capacitor models. However it would be nice to have a capacitor models with both the frequency and voltage dependence built-in.
@@Chris_Grossman Thanks for conversion. I think I understand now your points. For running the simulation I do not need a model. Since I assume a fixed frequency I just put an ideal cap R and L. For a deep analysis of capacitor simulations see www.ee.bgu.ac.il/~pel/pdf-files/jour143.pdf
Hi sir.
Could you make a video on modelling phase-shifted inverters and how to implement control and compensation circuit with commertial ICs? because all the phase-shifted ics that I found was only for dc dc converters.
Thank you.
Will see. Thanks for suggestion.
One thing missing from the presentation- the working point of the system. In EV, and in fact, in most motion systems, it's a very rare condition when both current and voltage on the motor are near the rated values and the system works near full power. In reality, usually, it's either we are going fast with little effort or we are pushing hard to accelerate, while the speed is low. Therefore the real optimum is different. Also the prices of ceramic capacitors are higher than the electrolytes, unfortunately.
Well,
1. The capacitor ripple is caused by the phase current, that is the torque, not the voltage (hence not a direct function of the power).
2. I design systems to withstand the maximum stress, not the average
@@sambenyaakov when the voltage is 20%, the current seen by the bulk capacitors is 20%, isn't it? At least in RMS terms. Frankly I am not sure how important is the peak, but my guess is that if the heat of the electrolyte is a problem, peak doesn't matter much.
As per maximum stress, i just mean that in certain systems marginal reliability is traded for cost, sometimes
@@lapserdak24 Again: the current ripple of the capacitors is a reflection of the phase current no matter what is the voltage. This video perhaps might help ua-cam.com/video/r_LmAsgfgrA/v-deo.html
@@sambenyaakov thank you very much for the video. This whole series would be helpful for me some 15 years ago :) and it's still interesting now.
However I would like to argue that even though the bulk capacitor current reflects the phase current, it is related to voltage as well. Its pretty obvious actually - neglect the losses, if motor voltage is 20% of the bus voltage then the bridge input (sitting on the full bus voltage) sees 20% of the current. Same amplitude, low duty cycle. Therefore the bulk capacitors at best see the 20%, and in fact less- part of the current comes from the battery.
So if we have a system where the battery is 60V and the motor never goes higher than 40V, the worst case will simply never occur.
@@sambenyaakov One year later i am working on a system that works on the exact spot i said was usually impossible :D
Thank you professor
Thanks
Better than my power electronics course
🙂🙏
@@sambenyaakov I feel like I need to review your videos. I will learn a good bit. Also get better in power electronics.
Very interesting
Thanks
@@sambenyaakov very welcome sir
Could please tell me, how to calculate the ripple voltage and capacitance, if there is 20kHz current component also present with equal magnitude?
"current component also present with equal magnitude?" ???
@@sambenyaakov I mean to say "what if other than 40kHz component also present in the capacitor current with significant magnitude"?
Eg: if there is an rectifier instead of battery, with very less cable inductance..
@@maheshkumarnandigama2756 Well, you ned to consider the combines current. I do not understand the difficulty.
@@sambenyaakov okay, but to calculate the Zc which frequency need to be considered?
@@maheshkumarnandigama2756 If one is, say, up to 30 percent of the other it can be neglected. Otherwise is is best examined by simulation in lieu of lengthy calculations.
how to analyse the capacitor ripple current using FFT
You need to carry time domain simulation and then FFT to see the spectrum.
👍👍👍💖👍👍👍
🙏🙂
Outstanding Job. 🙂
Thank you! 🙂
Sir,
Could you please share the simulatuion file ??
Sorry, I cannot spare the time.
BUS capacitors
?
Do you have a video covering AC voltage across class 1 MLCC capacitors? I bought some from LCSC rated for 630VDC at 15nF 1210 package size. They have pretty high Q factor, I think the datasheet specified minimum of 600? Pictures found here: imgur.com/gallery/8gYl5Qr
I put them to use in a DRSSTC tesla coil (a series resonant LC converter) and found that I could get some good performance from them, they did tend to crack, explode, and fail short-circuit, usually melting like glass due to the high voltage DC arc.
It seems that you are over stressing the caps. In UA-cam search window look for " sam ben- yaakov capacitor"
Check the dU/dt of your circuit and chose the capacitors accordingly. If their max dU/dt is not specified, don‘t use them. Also they have to stand the average current without getting to hot (short high current pulses of some us no problem mostly) There is a reason, most smd capacitors do not have any current spec: They suck at it. There are some RF COQ types on the market to meet the demand, but they are really expensive. Used in space, oil drills and warfare.