How to use vivado for Beginners | Verilog code | Testbench | Schematic View

Hi friend
in this video you will able to leran how to use Vivado ,you can learn writing module and testbench. do simulation verify the module,view schematic etc
for more video like this watch below
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what is vivado,how do i run vivado,vivado, vivado tutorial, vivado tutorial,

[@anandrajofficial1]

thank you all for love❤ ,keep supporting and keep liking & subscribing🙏.

[@ArjunNarula1122]

ua-cam.com/video/pTk1H50e8bI/v-deo.html

[@ArjunNarula1122]

Verilog projects playlist
ua-cam.com/play/PLUn6cqainH8jZxS3ppSGPi3rNScz9cFZf.html

[@moviesera5250]

Thanks my brother becoz of u i understood clear picture of using vivado I'm ur new subscriber

[@anandrajofficial1]

I am really very happy to hear this.
Thank you for comment.
Happy learning.

[@moviesera5250]

Bro I had some doubts in structural modelling can I get a video on it

[@anandrajofficial1]

@@moviesera5250 ua-cam.com/video/6TS8dozKXBs/v-deo.html
This xnor gate designed using nand gate in structural modelling design style.
If u didn't understand plz do comment.

[@balajis5170]

great video covering all basics

[@anandrajofficial1]

Thank you,plz keep supporting

[@kabandajamir9844]

So nice thanks crystal clear illustrations thanks

[@anandrajofficial1]

Keep learning 🙏🎉

[@mdfaizan1887]

Nice video ! this helped me a lot

[@anandrajofficial1]

Thank you for comment 🙏.

[@Jhon0034]

ty for this job

[@racram0444]

Thank you for this :)

[@ylakshmichandra9181]

I have a "Xilinx ZYNQ XC7Z010" board, sir. I'm new to Verilog; which board should I choose under Boards in the software? I'm using the Vivado 2021.2 programme.

[@anandrajofficial1]

During project creation it will give you option to select parts and board , select board and search for your FPGA board or after selecting parts you have to search for xc7z010. You will get it

[@riyazbajishaik1596]

Thanks for the video sir.
Sir, When I run the simulation it is taking forever.
It is basically stuck in run. Do you have any idea about this?

[@anandrajofficial1]

In test bench plz give $finish();
Before endmodule

[@riyazbajishaik1596]

@@anandrajofficial1
Sir, Thanks for the quick reply.
I did not include the test bench code.
I was thinking of giving inputs through the available Force constant option after running the simulation.

[@anandrajofficial1]

@@riyazbajishaik1596 then i think you have to stop simulation intentionally

[@jeffrinwilfred1887]

Thanks

[@zizo8737]

Brilliant

[@anandrajofficial1]

Thank you

[@DAEC_ShreyaS]

While runing simulation in test bench I will get as invalid top module wt shld i do

[@anandrajofficial1]

Check module name

[@lambroshalatsis6075]

When I press schematic it opens a package window and a Device window and not a schematic window what do I do ?

[@anandrajofficial1]

it does not happened with me so i exactly can't say anything what is issues,plz search in google.you may find solution.

[@mangapathiraju7198]

very nice...

[@anandrajofficial1]

Thank you

[@monsoonmallick9333]

Which edition of vivado is used ??

[@anandrajofficial1]

May be 2017 but it is the same for all versions

[@Nithish2604]

Sir after installing this , how much of space it occupied overall? I have only 80gb free disk space , can i download or not😢

[@anandrajofficial1]

if you want to only simulate on device like zedboard or then 55-60gb but if u want to go for different series like ultrascale and plus then 75gb

[@Nithish2604]

@@anandrajofficial1 it's just to learn the vivado tool recommended by my college is there any alternative tool to learn verilog with less memory is available? Pls show me some way!

[@anandrajofficial1]

@@Nithish2604 try vivado with lower version like 2017 below , and during installation don't select ultrascale , ultrascale plus and SoC device to reduce memory

[@Nithish2604]

@@anandrajofficial1 ok sir thanks for replying

[@shanmukharaobudumuru4471]

Sir If we want to display something in xilinix using verilog code ( like just writing hello world ) where can we see the display output in xilinix

[@anandrajofficial1]

Console panel is there

[@خفاش-ك7م]

thank you so much, I have a one question what is the purpose of clock ?

[@anandrajofficial1]

Cloçk in digital circuit used to synchronize the element so that it can work properly.

[@caleb7799]

Thanks for the easy to follow tutorial!

[@anandrajofficial1]

You're welcome!

[@nagasreevardhansharma722]

Sir is it applicable to 2022 version??
Please 🙏 reply

[@anandrajofficial1]

Yes

[@nagasreevardhansharma722]

@@anandrajofficial1 thank you 🙏🙏❤very much sir for replying
From Telangana, hyderabad

[@waelnour7147]

لو سمحت كلمة reg تظهر كلمة عادية وليست ملونة بالاحمر او الأزرق ؟!

[@VinayKumar-vi8bn]

While adding source vivado stucking no matter what the time taking, how to add source pls give a solution

[@yashviya3698]

Sirrrr....I want link to download it....can u plss give...tommorow is my practical exam

[@anandrajofficial1]

www.xilinx.com/support/download.html
go to this link , select the version and then click on
Xilinx Unified Installer 2022.2: Windows Self Extracting Web Installer . create account and then download

[@anjalin7935]

Hello it's taking too long to a create new project, is there any way I can fix it?? Kindly let me know if any..

[@anandrajofficial1]

Due to less RAM In pc,same happened with my pc too,.
How much RAM ur pc have?
If you want to do simulation only ,you can try with edaplayground.

[@anjalin7935]

@@anandrajofficial1 PC RAM is 8gb, actaully I needed to work on a project and I used to do small works on Icarus but I'll try once on edaplayground. Thank you!!

[@anandrajofficial1]

@@anjalin7935then it should work fine.for project vivado will be good.i don't know why it is slow in ur system.

[@menoxes1626]

does #10 mean wait for 10ns??

[@anandrajofficial1]

No it's not wait time, it's like first test input will be generated at 0 time and will continue till next time, now as it 10 hence previous test vector will be till 10ns and continue till next time

[@rookiegamer4657]

how to change font size in vivado text editor

[@anandrajofficial1]

Go to Tools->Settings then popup will come.in left side Tool Settings option will be there. In Tool Settings->Text Editor then expand text editor ->Fonts and colors then see right left size option is there. Then as per your comfort increase size.
In short
Tools->Settings->Text Editor->Fonts and colors
Then check top right side size option

[@valobhediya]

Can you please give me link to download this Xilinx Vivado please?

[@anandrajofficial1]

www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/archive.html

[@debabratobanik2103]

Which simulator is best and free for beginners for verilog hdl ??

[@anandrajofficial1]

Eda simulator and iverilog in my knowledge

[@siddharthst2712]

u can use intel quartus prime lite with modelsim intel fpga starter edition , both of which are free

[@pavanm6078]

how can I change the font size here???

[@anandrajofficial1]

Tool->option->fontmenu

[@pavanm6078]

@@anandrajofficial1 thank you

[@anandrajofficial1]

@@pavanm6078 most welcome

[@TravelandAdventure496]

link please

[@anandrajofficial1]

Already somewhere in the comments

[@mihiram592]

Critical error message during simulation

[@anandrajofficial1]

I am not familiar with this error please search in google you may get soln

[@rsf2671]

Sir one verilog code for register.

[@narsireddy_1]

Link sir

[@anandrajofficial1]

www.xilinx.com/support/download.html

[@kushalgourgonda3890]

Hiii sir please u can send me link 💕

[@maryamwaseem8633]

Version kon sa hai? 14.7 ya 14.2

[@anandrajofficial1]

2017.4

[@maryamwaseem8633]

Mtlb

[@maryamwaseem8633]

Istra btay 14.7 ya 14.2

[@anandrajofficial1]

@@maryamwaseem8633 17.4
www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/archive.html

[@maryamwaseem8633]

Ya xilinx hi hai ?

[@electroveda]

Thanks