Clock Skew Solved Problem (Digital Electronics) | Quiz # 500

In this video, for the given sequential circuit, the maximum allowable clock skew is calculated, and based on that maximum clock skew, the minimum required clock period is also calculated.
Here is the detail of the Quiz.
Subject: Digital Electronics
Topic: Clock Skew / Flip-Flop Timings
For more information about the clock skew, watch this video:
• What is Clock Skew ? T...
For more information about the setup time and hold time, check this video:
• Setup Time and Hold Ti...
For more videos on Digital Electronics, check this playlist:
• Digital Electronics
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The Quiz will be helpful to all the students of science and engineering for preparing for university or competitive exams (GATE, IES, etc.)
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Music Credit: www.bensound.com

[@allaboutelectronics-quiz]

For more information about the clock skew, watch this video:
ua-cam.com/video/HjfJNdPhJAE/v-deo.htmlsi=LySqlxsK8HnUPHki
For more information about the setup time and hold time, check this video:
ua-cam.com/video/3t8ndX2hqHA/v-deo.htmlsi=5u3-twKU2HIBib66
For more videos on Digital Electronics, check this playlist:
ua-cam.com/play/PLwjK_iyK4LLBC_so3odA64E2MLgIRKafl.html&si=Mgl5JcQqywvPdKlv

[@mayurshah9131]

Excellent 🎉🎉

[@aamir99204]

Sir what if there was another flip flop followed by these two flip flops? how will we then calculate that?

[@allaboutelectronics-quiz]

It depends how the circuit is connected. Whether the output of the first and second flip-flop are going into next combinational block. Or the output of only second flip-flop is going to the combinational logic block. In later case, you need to find Δ₂ - Δ₃ . In the earlier case, (where both outputs are going into next combinational block where third flip-flop is connected), you need to consider the TL and Ts of both combination block.

[@SatvikkumarRameshbhaiPatel]

4:39 Tcomb = 2ns. There's a mistake right?

[@allaboutelectronics-quiz]

TL and Ts both are Tcomb. One is maximum path length delay and another one is minimum path length delay in the combinational circuit. Here to find the minimum required clock skew corresponding to worst case scenario, minimum combinational delay (Ts) was considered.