Digital Circuits - Lecture 24: Systolic Arrays and Beyond (ETH Zurich, Spring 2017)
Вставка
- Опубліковано 10 лют 2025
- Lecture 24: Systolic Arrays and Beyond
Lecturer: Prof. Onur Mutlu (people.inf.ethz...)
Date: May 26, 2017.
Course webpage: www.syssec.ethz...
Slides (ppt):
www.ethz.ch/co...
Slides (pdf):
www.ethz.ch/co...
Thanks a lot for the course, Prof. Mutlu!
Thanks a lot for uploading these. Can you please somehow share the slides and lab exercise manuals too? It'd be a great help.
You can find the slides as well as all other course materials at:
www.syssec.ethz.ch/education/Digitaltechnik_17.html
We will later organize things better. But, please dig around a bit to get what you need.
thanks a lot : )
@@OnurMutluLectures Link isn't redirecting correctly!?
@@sundarramanp3057 I would suggest studying later versions of the course. Here is the UA-cam livestream playlist and course website from Spring 2021: ua-cam.com/video/LbC0EZY8yw4/v-deo.html safari.ethz.ch/digitaltechnik/spring2021/doku.php?id=schedule
I am interested in quantum computer architecture. Specifically, I have become led to these systolic arrays as a way I can seed tensor components for tensor mathematics on all elements simultaneously. And to connect the tensors between each another (perform a transform).
I would plan an FPGA connected directly to DDRAM (or SRAM) to store and set the weights and coefficients between pipeline execution elements.
What would you recommend for me in this case? Or have ideas?
I spoke too soon! This video answers my question perfectly!
How about encoding systolic arrays within a real-time 30fps, 120fps, or higher N-M image sensor with up to 48-bit color depth per pixel, and 3D channels? This throughput is very high and already part of the HDMI and MIPI standards as I understand.
How does the data move in weight stationary systolic array?
Nice explain thanks
What is difference between vector processor and systolic array processor.... please reply me