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Thank you! Havent seen any other videos about this topic. Can you hint where to find more information about caches? I need to introduce it in my H7 project.
Can we know the cost in CPU cycle to cache invalidate ? (Because it seems for simple transfert, it is quicker to do not have cache enable)
As per the ST's recommendation, cache must be enabled for the complicated projects.
nice video
TEX level is set at level 0. So I think it should be "Strongly order", not "Non Cachable".
Hmm good observation. Anyway strongly ordered and device memory, both are non cacheable regions.
Thank you! Havent seen any other videos about this topic. Can you hint where to find more information about caches? I need to introduce it in my H7 project.
Can we know the cost in CPU cycle to cache invalidate ? (Because it seems for simple transfert, it is quicker to do not have cache enable)
As per the ST's recommendation, cache must be enabled for the complicated projects.
nice video
TEX level is set at level 0. So I think it should be "Strongly order", not "Non Cachable".
Hmm good observation. Anyway strongly ordered and device memory, both are non cacheable regions.