VHDL Design Example - Structural Design w/ Basic Gates in ModelSim

[@shroomfungi373]

20:59 yow man. i wanna know what you'd press there to do that thing you did there

[@ndeutsch]

I have the problem of loading design in modelsim. Could you please say what's wrong with that? I'd really appreciate it.🙏

[@EngTawa]

I’m here to answer all your questions

[@miroabdalian2114]

Thank you. It helps a lot

[@jadasarchives]

@@unstoppableguy7896 the inverter gate has a single input defined as 'A', but we made three inverter components and mapped A of the inverter to A of system H for the first one, then A of the second inverter to B of system H, then A of the third inverter to C of system H. So we have an inverter per input signal A, B, C of system H

[@manmanual]

thanks mannn

[@ndeutsch]

Even when I double click on testbench