A pragmatic approach to improving your FPGA VHDL verification

A pragmatic approach to improving your FPGA VHDL verification
A good architecture is very important for FPGA design, but it is in fact equally important for verification of complex FPGA design. The verification architecture determines the verification efficiency and the product quality for complex designs. The difference between a good and a “normal” verification architecture could be many hundred hours, and for medium to complex designs even as much as a couple of thousand hours. The only good thing about this - is that you can easily do something about it. UVVM was made exactly for this and is free and open source - and used by 35-40% of all FPGA VHDL designers world-wide. A new ESA (European Space Agency) project has just been initiated to extend UVVM even further.