Now its been 7 years u upload the video. I m doing masters in power electronic and control . Starting i don't know about FPGA. Even my teacher teach be about FPGA. I didn't understand what he said. But U are genius, and i understand what is FPGA . I watch your first video. This this is my 4th video. I m gonna watch your all video. Thanks again .... keep it up.. sir ..
I love your videos man. I'm a new FPGA designer (and a mechE, so totally don't know electrical stuff) and this is really helping me to grasp the basics!
Thank you!!! for all of your videos. I mean for all of them. I'm Glad i subscribed and thank you "youtube" for providing the platform for seeing a one in a billion tutorial like this. Thanks man I really mean it.
Watched this for the second time, 6 months after the first, but now i have an FPGA dev board. light-bulb moment such a simple thing that as a traditional software programmer i never had to really worry about but this video really helps my understanding as i work on my FPGA project.
one way to think of it too, is the "gears" or clock are like tidal waves, coming in and out, with the polar harmony generating the "life" of the circuit. (this helps if your familiar with the concept that the early earth had a moon closer to it causing 100 mile tides, potentially creating life, just like the "life" of the circuit is created by this back and forth, on and off, clock motion. but anyways....... lol)
Great video. Hard to find information on this topic with UA-cam. A few comments though: A *register* is defined as a group of flip flops. Therefore, a 4-bit register is just a group of four flip flops, each one holding 1 bit of data. LUT? You mean a *truth table* . It's called a truth table whenever you're dealing with combinational circuits (the ones without storage elements). The moment you get into sequential circuits (circuits that have flip flops) it becomes a *state table* . I would replace "LUT" with "state table" because the accompanying diagram is called a state diagram, and then ultimately you produce the circuit diagram. A *state table* fully describes the operation of the sequential circuit. A state table contains a column for the present state, the inputs, the next state, and any outputs. But when you really get right down to it, the state table is just a truth table that includes present state as one of the inputs. It's also important to mention what a flip flop is. *A flip flop is storage for 1-bit of data, which can be either 0 or 1* . There are three types of flip flops commonly taught in digital logic courses: - D flip flop - T flip flop - JK flip flop *The D flip flop (data) is by far the easiest to understand:* - If you input 0, it stores 0 and outputs 0. - If you input 1, it stores 1 and outputs 1. *The T flip flop (toggle) operates as follows:* - If you input 0, the current state is maintained and outputted. (0 stays 0, 1 stays 1) - If you input 1, the current state toggles to its opposite and is outputted. (0 becomes 1, 1 becomes 0.) *The JK flip flop is the most advanced and most complex* . *It has TWO inputs (J and K) plus the clock:* - If J = 0 and K = 0: Current state is maintained and outputted. (0 stays 0, 1 stays 1) - If J = 1 and K = 0: Current state is set to 1 and outputted. - If J = 0 and K = 1: Current state is reset to 0 and outputted. - If J = 1 and K = 1: The current state toggles. (0 becomes 1, 1 becomes 0). Therefore, the JK flip flop can perform the operations of both the D flip flop and the T flip flop in one. Why use different flip flops? Well, sometimes the logic is a lot more complex to implement with one type of flip flop than it is with another. That can greatly affect the speed of the circuit.
thanks for the videos! and thank you for your website too! i dont really understand why so many people work so hard to put out good work like this for everyone to use, when so many people dont even use it. they want better jobs and a better life yet these free resources go ....... anyway ..... //end of rant. thank you!
Superb information. Will you guide to use flip flop's in making a model train signalling system involving only 2 leds (red and green) per flip flop cascaded so that each flip flop triggers the next one so that green becomes red once the train passes the sensor say magnetic reed switch on the track.
thanx one question please! In the single and simple example of a Dflip-flop if the input data D is changing exactly with a rising cycle clock CLK, does the output Q of the DFF will perceive it or not?
Tony Sznabel Hi, I'm not the author of those videos, but here's my guess: Just as in the author explains in the case of two flip flop, "In the real physical world, it takes some time for the signal to rise", and in that same example Q2 is the data input of the second flip flop. My guess is, the time duration of that "some time to rise" is the sum of two times: T1, the time for the signal to propagate from Q1 to D2, like it's a cord. then, T2 is the necessary time for the signal to rise from low to high level. Why, in the real world, is there a necessary time for the signal to rise from a level to another level? Because this signal is never actually "square", it is an electrical current whose value is continuously changing, and here it is contiously rising from one value, to another. To convinced yourself, just say to yourself that the current value at a given instant CANNOT have more than ONE value, so the curve at the rise CANNOT be vertical. drawing it vertical is an approximation, just meaning the slope's gradient of tangent is very high, "almost vertical in the neighborhood". Very, very sloppy. In other words, current's value rises so fast, its curve looks like vertical at that point. Alright, so in the example with 2 flip flops, author says that when clock rise and Q1 rise occur at the same instant, T1 + T2 is big enough so that Q2 stays low, and he adds, "this is dued to what's called propagation time". So your question is "what happens to Q2 if T1 = 0?", isn't it? What I'm doing here, is shifting your exact question as closely as possible to the author's vocabulary, so that I can use the exact same reasoning as a mechanism to come to a conclusion, based on what the authored gives. Okay, so here 's my answer: the author, again, says that if Q2 stays low, it is dued to something reaaaally important called propagation time. Then my guess is: the answer to your question is that what will happen is kind of random, un predictible, and most importantly, IT DOESN'T matter, we don't care, what we care about (to understand FGPA's) is what happens when there's a T1 : T1 is not zero. Futhermore, T1 is considered non zero when it's big enough so that the system behaves with that VERY IMPORTANT thing that is the delay between Q1 and Q2: meaning the system is designed to behave WITH such a delay. Designers of FGPA's WANT that delay to be part of the behaviour of the system they designed. there's a treshold where that delay appears, what is the exact treshold we don't care, we'll eventually just tune it to some other system's tuned value, so that we get the desired collaboration between systems. To end with this, the value we are going to tune is a physical value measured for the electrical current, that one value that determines the slope of the rise of the (curve of the) current's voltage from low level to high level. Thank you very much for your question, it had think the whole thing over! And thank you to the author of the video for making and broadcasting them! Jean-B.
Probably not... There's a thing called setup time that is required. Meaning the input D needs to be stable for some amount of time before the rising clock edge comes along. This is a subject for a future video. I already wrote about it on www.nandland.com. Check the FPGA-101 page.
The output of the flip-flop (Q is output) changes high or low depending on the D input. The Flip-Flop "looks" at the input when the rising edge of the clock comes along. This happens to all flip-flops in the system at the same time. Hope that's helpful.
There are some real world delays associated with changing flip flops, yes. Look up setup time, hold time, and propagation delay. But this waveform is exactly what you'll see in a simulation. Simulations are perfect case (no delays).
A flip-flop is a type of RAM. In an FPGA RAM is most often created with either Flip-Flops or Block RAMs. I made a video on what a Block RAM is if you're unfamiliar with those. In general, flip flops are for small amounts of storage, Block RAMs are for storing large amounts of data. ua-cam.com/video/fqUuvwl4QJA/v-deo.html
i'm sorry but i'm at 23:05 and you still haven't referenced how flip flops are used in FPGAs? if we're learning about FPGA's then the chances are that most of us have covered what a flip flop is already.. Other people seem to like the video though so thanks anyways
Thank you SO much! I have been learning fpga's and verilog for a long time now at CU Denver and am going to watch your whole series bc I just seem to be struggling so much. You are so much more helpful than my professor and I really want to learn!
If there's a propagation delay in Q1, why not on D1? I can understand the second flip-flop being delay 1 clock cycle. But that's not the same as the sampling propagation delay is it?
Now its been 7 years u upload the video. I m doing masters in power electronic and control . Starting i don't know about FPGA. Even my teacher teach be about FPGA. I didn't understand what he said. But U are genius, and i understand what is FPGA . I watch your first video. This this is my 4th video. I m gonna watch your all video. Thanks again .... keep it up.. sir ..
We did these basics in cs courses, but you fill the gaps in my knowledge very nicely. Those bits of intuition you give make it a lot easier to digest
I love your videos man. I'm a new FPGA designer (and a mechE, so totally don't know electrical stuff) and this is really helping me to grasp the basics!
More videos!!! These are great. It's like FPGA for dummies.
Thank you!!! for all of your videos. I mean for all of them. I'm Glad i subscribed and thank you "youtube" for providing the platform for seeing a one in a billion tutorial like this. Thanks man I really mean it.
I've been struggling to understand the concept of flip-flop, but now all I can say is thank you.
Watched this for the second time, 6 months after the first, but now i have an FPGA dev board. light-bulb moment such a simple thing that as a traditional software programmer i never had to really worry about but this video really helps my understanding as i work on my FPGA project.
Thanks for your videos, they're great! I am a little worried about how much ink is getting on your shirt, though.
I confuse how to save date with D when D changing with clock in H state.
Ur teaching pattern is quite interesting.. And also speaking style is very pleasant. Well done thank you 🙂💐
The flip flop and rising edge of the clock was so well explained, thanks 🙏
Thank you for making these videos, they are awesome and the way you explain things are awesome.
very useful video. I am new to FPGA, but it is very easy to understand what you say. Thank you.
Thanks for making this videos they are great and very easy to understand even for me that Im not a native speaker
These videos are great. I was able to get a really clear understanding of the flip flop after this video.
it is old, but still helping people. It is really helpful.
plz add more video :) can't wait!
Q2 is logic low because of propogation delay at second rising edge.Q does not change at the same time as the clock. It has a small delay each time.
Clear and helpful. Thank you very much!
Very good explanation. Still relevant today!
Great Videos! I am stil hoping for more in the future!
one way to think of it too, is the "gears" or clock are like tidal waves, coming in and out, with the polar harmony generating the "life" of the circuit. (this helps if your familiar with the concept that the early earth had a moon closer to it causing 100 mile tides, potentially creating life, just like the "life" of the circuit is created by this back and forth, on and off, clock motion. but anyways....... lol)
I have not many time to learn, but I will try understand it. I love electronics :-)
Great video. Hard to find information on this topic with UA-cam. A few comments though:
A *register* is defined as a group of flip flops. Therefore, a 4-bit register is just a group of four flip flops, each one holding 1 bit of data.
LUT? You mean a *truth table* . It's called a truth table whenever you're dealing with combinational circuits (the ones without storage elements). The moment you get into sequential circuits (circuits that have flip flops) it becomes a *state table* . I would replace "LUT" with "state table" because the accompanying diagram is called a state diagram, and then ultimately you produce the circuit diagram.
A *state table* fully describes the operation of the sequential circuit. A state table contains a column for the present state, the inputs, the next state, and any outputs. But when you really get right down to it, the state table is just a truth table that includes present state as one of the inputs.
It's also important to mention what a flip flop is. *A flip flop is storage for 1-bit of data, which can be either 0 or 1* .
There are three types of flip flops commonly taught in digital logic courses:
- D flip flop
- T flip flop
- JK flip flop
*The D flip flop (data) is by far the easiest to understand:*
- If you input 0, it stores 0 and outputs 0.
- If you input 1, it stores 1 and outputs 1.
*The T flip flop (toggle) operates as follows:*
- If you input 0, the current state is maintained and outputted. (0 stays 0, 1 stays 1)
- If you input 1, the current state toggles to its opposite and is outputted. (0 becomes 1, 1 becomes 0.)
*The JK flip flop is the most advanced and most complex* . *It has TWO inputs (J and K) plus the clock:*
- If J = 0 and K = 0: Current state is maintained and outputted. (0 stays 0, 1 stays 1)
- If J = 1 and K = 0: Current state is set to 1 and outputted.
- If J = 0 and K = 1: Current state is reset to 0 and outputted.
- If J = 1 and K = 1: The current state toggles. (0 becomes 1, 1 becomes 0).
Therefore, the JK flip flop can perform the operations of both the D flip flop and the T flip flop in one.
Why use different flip flops? Well, sometimes the logic is a lot more complex to implement with one type of flip flop than it is with another. That can greatly affect the speed of the circuit.
That's great. Thanks for easy way in explanation .
Thanks Russel, very well explained.
Excellent introduction
Great info! Thank you
thanks mate you saved my test
Thank you so much!
You save my life
Thank you for this video!
More understandable than my penn state teacher. Thank you!
Ian F Penn State here too. What year do you take this class?
Excellent man, thanks a lot!
thank you man, wish u make more tutorials
Well explained my man.
Best explanation ive seen so far :p
Las esplicaciones son faciles de entender. seria muy conveniente poner una numeracion que indique una secuencia de videos de inicio al mas reciente.
clear explanation
thanks for the videos! and thank you for your website too! i dont really understand why so many people work so hard to put out good work like this for everyone to use, when so many people dont even use it. they want better jobs and a better life yet these free resources go ....... anyway ..... //end of rant. thank you!
Digital Techniques ... How do you write in software?
Good explaination.
Thanks, It was so good
Superb information. Will you guide to use flip flop's in making a model train signalling system involving only 2 leds (red and green) per flip flop cascaded so that each flip flop triggers the next one so that green becomes red once the train passes the sensor say magnetic reed switch on the track.
Great work, keep it up!
thanks man, very good explanation . keep up
The process control industry mostly uses SR-FlipFlops. No clocks just states!
For ASICs you mean?
You Are Amazing !!
You are goodlooking :))
U are doing a great job!
if you look closely you'll actually see that he is not standing but is rather sitting on something
what you describe is a latch not a flipflop though it's confusing because often the words are interchanged
So its SISO type registor the 3rd example
You are great! Thank you.
thanx
one question please!
In the single and simple example of a Dflip-flop
if the input data D is changing exactly with a rising cycle clock CLK, does the output Q of the DFF will perceive it or not?
Tony Sznabel
Hi, I'm not the author of those videos, but here's my guess: Just as in
the author explains in the case of two flip flop, "In the real physical
world, it takes some time for the signal to rise", and in that same
example Q2 is the data input of the second flip flop. My guess is, the
time duration of that "some time to rise" is the sum of two times: T1,
the time for the signal to propagate from Q1 to D2, like it's a cord.
then, T2 is the necessary time for the signal to rise from low to high
level. Why, in the real world, is there a
necessary time for the signal to rise from a level to another level?
Because this signal is never actually "square", it is an electrical
current whose value is continuously changing, and here it is contiously
rising from one value, to another. To convinced yourself, just say to
yourself that the current value at a given instant CANNOT have more than
ONE value, so the curve at the rise CANNOT be vertical. drawing it
vertical is an approximation, just meaning the slope's gradient of tangent
is very high, "almost vertical in the neighborhood". Very, very sloppy.
In other words, current's value rises so fast, its curve looks like
vertical at that point. Alright, so in the example with 2 flip flops,
author says that when clock rise and Q1 rise occur at the same instant,
T1 + T2 is big enough so that Q2 stays low, and he adds, "this is dued
to what's called propagation time". So your question is "what happens to
Q2 if T1 = 0?", isn't it? What I'm doing here, is shifting your exact
question as closely as possible to the author's vocabulary, so that I
can use the exact same reasoning as a mechanism to come to a conclusion,
based on what the authored gives. Okay, so here 's my answer: the
author, again, says that if Q2 stays low, it is dued to something
reaaaally important called propagation time. Then my guess is: the
answer to your question is that what will happen is kind of random, un
predictible, and most importantly, IT DOESN'T matter, we don't care,
what we care about (to understand FGPA's) is what happens when there's a
T1 : T1 is not zero. Futhermore, T1 is considered non zero when it's
big enough so that the system behaves with that VERY IMPORTANT thing that
is the delay between Q1 and Q2: meaning the system is designed to
behave WITH such a delay. Designers of FGPA's WANT that delay to be part
of the behaviour of the system they designed. there's a treshold where
that delay appears, what is the exact treshold we don't care, we'll
eventually just tune it to some other system's tuned value, so that we
get the desired collaboration between systems. To end with this, the
value we are going to tune is a physical value measured for the
electrical current, that one value that determines the slope of the
rise of the (curve of the) current's voltage from low level to high
level.
Thank you very much for your question, it had think the whole thing
over! And thank you to the author of the video for making and
broadcasting them!
Jean-B.
Probably not... There's a thing called setup time that is required. Meaning the input D needs to be stable for some amount of time before the rising clock edge comes along. This is a subject for a future video. I already wrote about it on www.nandland.com. Check the FPGA-101 page.
I understood Rising edge and Falling edge a little. Never Dont understand diagrams data exchange
How would D change to high before the rising edge? Would the data not be in sync with the clock?
The output of the flip-flop (Q is output) changes high or low depending on the D input. The Flip-Flop "looks" at the input when the rising edge of the clock comes along. This happens to all flip-flops in the system at the same time. Hope that's helpful.
Dude you’re awesome
can u please put some commercial level work what designers doing at office from scratch
Big thanks.
Thank you! You are awesome
One question though: Q2 is one cycle shifted w.r.t. Q1, but Q1 is not exactly once cycle shifted to D, right? It is actually like 3/4 cycle shifted?
Xinxing Wang Right, but D does not change along with the clock rising edge. In this example we assumed that D can change at any time.
There are some real world delays associated with changing flip flops, yes. Look up setup time, hold time, and propagation delay. But this waveform is exactly what you'll see in a simulation. Simulations are perfect case (no delays).
so Q behaves like the output of an AND gate??
thanks for the video
Rewatching these videos is critically important.
perfect video thx bro
why does Q always start low?
It usually does. You can set it to non zero value if you need to.
More Videos please.
Make a playlist
Very good :)
Great video, thanks for the help!
What is a hardware nerd's favorite energy drink?
Field Programmable Gatorade.
Without flip flops you wouldn't have almost any electronic device in the world.
it is nice thanks
Thank you handsome
Data between two clock edge are LOST !
a flip flop is when u flip me on that DEE
So a flip-flop is similar to RAM?
A flip-flop is a type of RAM. In an FPGA RAM is most often created with either Flip-Flops or Block RAMs. I made a video on what a Block RAM is if you're unfamiliar with those. In general, flip flops are for small amounts of storage, Block RAMs are for storing large amounts of data. ua-cam.com/video/fqUuvwl4QJA/v-deo.html
ok awesome, just glad I didn't have some glaring mis-conception.
Thanks, I'll take a look now.
how to get job ? i made 32 bit alu
First before flip flop I would like to know what is a FPGA
K. ua-cam.com/video/CfmlsDW3Z4c/v-deo.html
Actually the clock in a microproccessor does go to every Flip-Flop, otherwise there wouldnt be any flipping or flopping ;)
an active state component, flip-flop, is insanity, should be pure state object, non-powered
sample the contents, not transmit them all the time, like your mouth is repeating all the time
pulse clock, wave, not repeating clock
Please hindi dub this vedio
now he got the eraser after seeing the previous comments
Please teach some discipline for your sis, Sir.
YOU FORGOT THE CLOCK . . . Do you assume we can pull it out of the air? Your video is only conceptual.
shut up, meg
@@Gunth0r Why? Are you his sister? What's this have to do with you PoppyPants?
You explained this the same way a college buddy would. You're really good at this.
Good job dude, nice explained and easy to follow. Very interesting to me since I am new to FPGA. Looking forward to your next video!
Your talking way is very comfortable to me. Update more videos.
I like FPGA.
i'm sorry but i'm at 23:05 and you still haven't referenced how flip flops are used in FPGAs? if we're learning about FPGA's then the chances are that most of us have covered what a flip flop is already.. Other people seem to like the video though so thanks anyways
Thank you SO much! I have been learning fpga's and verilog for a long time now at CU Denver and am going to watch your whole series bc I just seem to be struggling so much. You are so much more helpful than my professor and I really want to learn!
Your tutorials has been great! You provide layman explanation on niche technical terms, it is newbie friendly! Thanks for your effort.
Easy to follow, good explanations. Subscribed. Please more videos :)
Thanks for the video , please continue your good work , believe me they are very helpful .
It is really interesting. Thank you
thank for your videos they are really helpful .. just i want to say that i use NE555 like a clock
Thanks this really cleared up a lot of stuff.
I’m struggling to understand what your video has to do with FPGA’s. It’s all about a basic explanation od one of the flip-flops…
If there's a propagation delay in Q1, why not on D1? I can understand the second flip-flop being delay 1 clock cycle. But that's not the same as the sampling propagation delay is it?
Why is Tom Hardy teaching me about flip flops?
Sir,please post more videos. Your explanations are really easy to understand. Helped alot. Thank you.
Seriously? Kitna Padhai karega be? :/ . should i even be surprised to see you here... Jokes apart, thanks for the brilliant explanation man
Great Tutorials Sir Please do more. Thanks!!