Thanks for that. A promotion! You’ve started watching at the right time. The next video in this series (due next week) will be the main bring-up video where we see if it all works.
I just found your videos. The thought of building a 6502 from scratch sounds very appealing. My first computer was a SYM-1 running a 6502, so I have a long-standing love for the old chip. As for your comment about the original architecture being too complicated, challenge accepted! 😃 I'd love to build a replica at least at the block level that runs in real time and is identical at the cycle level.
I just finished building Ben Eater’s SAP-1 (and I built his 6502 kit before that). So I really enjoyed this. The fact that the ‘574 has all the input and output pins lined up (and have 8 bits) is really encouraging for making an easier build. I could see designing and ordering a PCB with just 8 parallel lines to get started as a way to begin.
Great video. I like the soldering technique you demonstrate at the end. I’ve used wire wrap for my much smaller projects, and sometimes I’ve used your technique for applying short strips of insulation, but I’ve never done it at the scale you need for a bus layout. I’ll keep that in mind.
Glad you like it. Yeah, the trick is to pre-stretch the wire a little, just enough to allow the insulation to slide. Not too much though, you don't want to fracture the wire.
I was really hoping for your inverter bus contention demo to result in the magic smoke escaping. I don't know why except perhaps to feel better about the times I have done it by accident. BTW a good explanation of tri state logic.
Glad you liked it. Actually, short of applying the power backwards, i've found the 74HC series pretty hard to kill, more robust than 74LS. Maybe that's just anecdotal i don't use 74LS much these days.
Worrying about that made me quadruple check every bit on the EEPROMs on the Ben Eater SAP-1 I built. But then I plugged the EEPROM in upside down and it got very hot (I measured 160F on the top of the EEPROM and that was after I had unplugged it for a minute). But everything survived that mistake lol
Amazing stuff. At the same time , I want the entire series to be available to watch now, but I'm also happy to see that it isn't because i wouldn't get anything else done while I was watching it.
MORE! I do my prototypes in a similar way, using wire wrap wire, but the way of getting rid of insulation is different for me, I just melt right through it with the soldering iron (putting a solder blob on the socket or IC leg I heat it up and wind the wire around the hot leg) - looks awful, but works. I mostly do 'slow' stuff though, multiplexing I/O from a uC, or maybe I2C. But this should work to at least a couple of MHz, it's not far from true wire wrap technology (excluding the unobtanium sockets and the wire wrap gun/pen), and that stuff could run real fast. The more chaos in the wiring the better though, I heard.
Sometimes i do melt the insulation, especially if i've cut it to the wrong length. The trick with this technique is that you need to pre-stretch a wire a little. It's a bit of a balancing act. If the insulation melts too easily, i'm worried about the insulation fusing together (which i've had happen) and potentially causing a short. I like the Kynar wire which is actually quite hard to melt, but it doesn't seem to fuse. Yep apparently a rat's nest runs faster than the way I wire, but you probably want a PCB to clock it really fast.
Good explanation of tri-state logic, but I was thrown off by the following question: If all registers are connected to the same bus, how do you choose which register is written to? In Ben Eaters SAP-1 design, all registers are connected to the same clock, but have individual write-enable inputs. It is only in the second video of this series where it seems to become apparent that this SAP-6502 design works differently: The inputs of all registers are connected to the same bus, there is no write-enable pin on the registers, and the control logic has to make sure that it ONLY clocks the target register to store the value which is currently on the bus.
Yep, it was a bit of an engineering trade-off. Ideally, these octal buffers would have a clock, and a write enable and an output enable. Unfortunately, they don't and you get to choose two! I decided on using octal d-type flip-flips with an output enable would be better in this case because so many of them connect to the W-bus. Ben Eater, decided the other way, but he has to add in a tri-state buffer per register.
@@DrMattReganwhat is the fuss with the clock. RAM was async till the Sega32x in 1994. No one expects a clock like there . That is no one but students who learn RTL .
I think part of Ben's accessibility is that for each statement he makes, he reiterates it 2-4 times, with slight syntactic changes each time, accompanied by 1-2 visual aids, before moving on. Kinda like Sesame Street.
I have on question about registers, at the end of series we have implemented all the instructions of 6502 using only few of registers in our model. Then why it is not running as same speed as 6502, why dont we use as many registers as we want ? wont it will be beneficial for us ? also is it not possible to replicate everything in 6502 in our build?
Good questions, I think we use a similar number of registers compared to the 6502, but (nearly) everything has to go through the single w-bus, where as the actual 6502 has a more complex bus structure. In effect it can functions in 1 clock that take us several clocks. This was done on purpose though, because the idea isn't to exactly replicate the 6502, the idea is to show that something as simple as the SAP1 can be made to run 6502 code. At the end of the day, if we use faster chips we can still beat the original 6502, even though we have more clocks per instruction.
@@DrMattReganhaving already rolled my own, im sure it'd be worth looking into if i could do it *better* thanks for the content, people like you make people like me possible (no school, all self taught)
Never actually seen Malvino's book before (I must have been daydreaming or something, when Ben Eater showed it).... But just look at that cover design! They don't design book covers like that anymore!
Sir - you are much much more than 0.1x Ben Eater (Blessed Be He😃) That sort of comparison is invidious, and contributes nothing. Ben's fantastic project (in the philosophy sense) takes a relative novice to the point of a reasonably thorough understanding of the basics of cpu and computer architecture. Yours is to use that developed understanding as your starting point and take it further. (and probably to have some fun 🙂). I love it !
Thanks Mike, I really appreciate it. You've hit the nail on the head. Ben Eater does a great job and I think his work stands on its own merits. My plan was to advance what he has done for those interested in taking it further. I want this knowledge to be freely available and not stuck behind some paywall.
Welcome and enjoy. The B-Roll is tricky, because i was told the Turing6502 series was very "dry", so i tried to lighten it up a bit. If it's any consolation, i've disabled midroll advertisements, so the video clips would normally be ads.
@@AK-vx4dy Monster6502? This is a bit different. It’s not a replica, it’s a simplified version. It uses a simplified architecture, but it requires more clocks per cycle as a result.
Got a much better idea. Write it up in VHDL and synthesize to an FPGA. A single chip solution. Learn some modern design techniques and use modern technology.
@@DrMattRegan No because you're teaching digital logic skills, not software. Two totally different skill sets. It is good to have an understanding of both, particularly when a function can be implemented in either software or hardware and that is a decision the engineer needs to make.
I may use FPGAs later on if i go down the pathway of building a VIC 2 chip or (much later) denise, agnus and paula. But this series was meant to lead off from Ben Eater's SAP-1 series using the same technology.
@@deang5622before the pipeline, CPUs seemed to have worked in a rather sequential fashion. Especially the Z80 has many machine cycles per instruction. Multiple T cycles . Which again have two non-overlapping phases.
Don't do yourself down mate, you're at least 0.2 of an Eater! And worth watching way more than most!
Thanks for that. A promotion! You’ve started watching at the right time. The next video in this series (due next week) will be the main bring-up video where we see if it all works.
In-depth videos like this are a treat. Will be amazing to see how it ends up!
Glad you enjoy it, working on the next ones now.
I just found your videos. The thought of building a 6502 from scratch sounds very appealing. My first computer was a SYM-1 running a 6502, so I have a long-standing love for the old chip.
As for your comment about the original architecture being too complicated, challenge accepted! 😃 I'd love to build a replica at least at the block level that runs in real time and is identical at the cycle level.
@@briancampbell179 welcome. Excellent, have a crack at building one. It may also be worth watching the Turing6502 series.
@@DrMattRegan , shall do.
I just finished building Ben Eater’s SAP-1 (and I built his 6502 kit before that). So I really enjoyed this. The fact that the ‘574 has all the input and output pins lined up (and have 8 bits) is really encouraging for making an easier build. I could see designing and ordering a PCB with just 8 parallel lines to get started as a way to begin.
Sounds good, i'll be doing some videos with schematics soon.
Looking forward to see how you pull this one off!
Thanks, you probably know more than anyone else, how tricky it is to get everything right with the 6502
Great video. I like the soldering technique you demonstrate at the end. I’ve used wire wrap for my much smaller projects, and sometimes I’ve used your technique for applying short strips of insulation, but I’ve never done it at the scale you need for a bus layout. I’ll keep that in mind.
Glad you like it. Yeah, the trick is to pre-stretch the wire a little, just enough to allow the insulation to slide. Not too much though, you don't want to fracture the wire.
I was really hoping for your inverter bus contention demo to result in the magic smoke escaping. I don't know why except perhaps to feel better about the times I have done it by accident. BTW a good explanation of tri state logic.
Glad you liked it. Actually, short of applying the power backwards, i've found the 74HC series pretty hard to kill, more robust than 74LS. Maybe that's just anecdotal i don't use 74LS much these days.
Worrying about that made me quadruple check every bit on the EEPROMs on the Ben Eater SAP-1 I built. But then I plugged the EEPROM in upside down and it got very hot (I measured 160F on the top of the EEPROM and that was after I had unplugged it for a minute). But everything survived that mistake lol
Amazing stuff. At the same time , I want the entire series to be available to watch now, but I'm also happy to see that it isn't because i wouldn't get anything else done while I was watching it.
Working on the next one this weekend - the wiring is done, it just takes a while to edit the videos.
MORE!
I do my prototypes in a similar way, using wire wrap wire, but the way of getting rid of insulation is different for me, I just melt right through it with the soldering iron (putting a solder blob on the socket or IC leg I heat it up and wind the wire around the hot leg) - looks awful, but works.
I mostly do 'slow' stuff though, multiplexing I/O from a uC, or maybe I2C.
But this should work to at least a couple of MHz, it's not far from true wire wrap technology (excluding the unobtanium sockets and the wire wrap gun/pen), and that stuff could run real fast.
The more chaos in the wiring the better though, I heard.
Sometimes i do melt the insulation, especially if i've cut it to the wrong length. The trick with this technique is that you need to pre-stretch a wire a little. It's a bit of a balancing act. If the insulation melts too easily, i'm worried about the insulation fusing together (which i've had happen) and potentially causing a short. I like the Kynar wire which is actually quite hard to melt, but it doesn't seem to fuse.
Yep apparently a rat's nest runs faster than the way I wire, but you probably want a PCB to clock it really fast.
Damn, you just invented RISC processors! :-) really enoyed your video and project. Thank you.
Enjoy, you might like the Turing6502 series too.
Excellent! Can't wait to see your sequencer. I'm sure it's more original that using a Ubicom SX28 clocked at 75 MHz. 🤪
Good explanation of tri-state logic, but I was thrown off by the following question: If all registers are connected to the same bus, how do you choose which register is written to? In Ben Eaters SAP-1 design, all registers are connected to the same clock, but have individual write-enable inputs. It is only in the second video of this series where it seems to become apparent that this SAP-6502 design works differently: The inputs of all registers are connected to the same bus, there is no write-enable pin on the registers, and the control logic has to make sure that it ONLY clocks the target register to store the value which is currently on the bus.
Yep, it was a bit of an engineering trade-off. Ideally, these octal buffers would have a clock, and a write enable and an output enable. Unfortunately, they don't and you get to choose two! I decided on using octal d-type flip-flips with an output enable would be better in this case because so many of them connect to the W-bus. Ben Eater, decided the other way, but he has to add in a tri-state buffer per register.
@@DrMattReganwhat is the fuss with the clock. RAM was async till the Sega32x in 1994. No one expects a clock like there . That is no one but students who learn RTL .
I think part of Ben's accessibility is that for each statement he makes, he reiterates it 2-4 times, with slight syntactic changes each time, accompanied by 1-2 visual aids, before moving on. Kinda like Sesame Street.
Yes, Ben has exceptional teaching skills. I'm thinking of doing a simpler series based on relays, so i'll keep this in mind.
ty for the awesome content.
Glad you enjoy it!
I have on question about registers, at the end of series we have implemented all the instructions of 6502 using only few of registers in our model.
Then why it is not running as same speed as 6502, why dont we use as many registers as we want ? wont it will be beneficial for us ?
also is it not possible to replicate everything in 6502 in our build?
Good questions, I think we use a similar number of registers compared to the 6502, but (nearly) everything has to go through the single w-bus, where as the actual 6502 has a more complex bus structure. In effect it can functions in 1 clock that take us several clocks. This was done on purpose though, because the idea isn't to exactly replicate the 6502, the idea is to show that something as simple as the SAP1 can be made to run 6502 code.
At the end of the day, if we use faster chips we can still beat the original 6502, even though we have more clocks per instruction.
Very informative and interesting
Glad you enjoyed it!
Ben eater * 0.10 is still college level lectures
DEFINITELY still worth watching
Thanks, Enjoy. Don't forget there is a whole series on writing the microcode as well.
@@DrMattReganhaving already rolled my own, im sure it'd be worth looking into if i could do it *better*
thanks for the content, people like you make people like me possible (no school, all self taught)
Never actually seen Malvino's book before (I must have been daydreaming or something, when Ben Eater showed it).... But just look at that cover design! They don't design book covers like that anymore!
If you poke around online you can find a pdf of the book. They are pretty expensive now for a physical copy. The trick now is thumbnail design!
What is a effective low/high register?
The Effective Address registers are for storing/computing the address of the data for various addressing modes.
Sir - you are much much more than 0.1x Ben Eater (Blessed Be He😃) That sort of comparison is invidious, and contributes nothing. Ben's fantastic project (in the philosophy sense) takes a relative novice to the point of a reasonably thorough understanding of the basics of cpu and computer architecture. Yours is to use that developed understanding as your starting point and take it further. (and probably to have some fun 🙂). I love it !
Thanks Mike, I really appreciate it. You've hit the nail on the head. Ben Eater does a great job and I think his work stands on its own merits. My plan was to advance what he has done for those interested in taking it further. I want this knowledge to be freely available and not stuck behind some paywall.
I've just found your videos and they're great. would really love it if you dropped the silly movie clips though, they are really distracting.
Welcome and enjoy. The B-Roll is tricky, because i was told the Turing6502 series was very "dry", so i tried to lighten it up a bit. If it's any consolation, i've disabled midroll advertisements, so the video clips would normally be ads.
Should be, some guys decoded fully die shot and done full schematic and even build one from transitors with blinking diodes
@@AK-vx4dy Monster6502? This is a bit different. It’s not a replica, it’s a simplified version. It uses a simplified architecture, but it requires more clocks per cycle as a result.
@@DrMattRegan They lied to me? 😡 and this in browser simulation is 1:1?
@@AK-vx4dy not quite sure what you mean? What in browser simulation?
@@DrMattRegan The Visual 6502
@@AK-vx4dy oh OK. The Monster6502 was based on the visual 6502. This is different. Make sure you watch the series on the microcode too!
My university portal was called sap
Ha, I actually got it from Ben Eater, i kind of inherited the name.
No wirewrap, then? lol
Nah, i've used point-to-point wiring for so long i find it easier.
you voice sounds like a robot
@@maxbursell3513 yes, I don’t have a studio, so I need the adobe filters to clean up the audio. What did you think of the content?
@@DrMattRegan Hi, Very awesome content. really like it. :)
Got a much better idea. Write it up in VHDL and synthesize to an FPGA. A single chip solution.
Learn some modern design techniques and use modern technology.
Why not use an RP2040 if you're using modern chips. Cheaper and easier to get.
@@DrMattRegan No because you're teaching digital logic skills, not software.
Two totally different skill sets.
It is good to have an understanding of both, particularly when a function can be implemented in either software or hardware and that is a decision the engineer needs to make.
I may use FPGAs later on if i go down the pathway of building a VIC 2 chip or (much later) denise, agnus and paula. But this series was meant to lead off from Ben Eater's SAP-1 series using the same technology.
@@deang5622before the pipeline, CPUs seemed to have worked in a rather sequential fashion. Especially the Z80 has many machine cycles per instruction. Multiple T cycles . Which again have two non-overlapping phases.
@@ArneChristianRosenfeldt Doesn't actually address the issue I raised.