FPGA Based DC DC Buck Converter

[@ЕвгенийШепард-р2х]

Excellent! Well done!

[@Ma_X64]

I don’t know if it’s Spanish or Portuguese, but it sounds beautiful. I like.

[@AlonsoDT]

Hola Miguel, gracias por el video, está muy bueno. Me puedes compartir los diagramas de bloques digitales que muestras a partir de 5:40? Los diagramas son de alguna fuente en especial, o los has elaborado tu mismo?
Saludos.

[@dufflepod]

Great video

[@miguelprado7092]

Glad you enjoyed it

[@nysseexaucekaya8620]

Hello very nice video. How can I get the vhdl code and the hardware design please?

[@mikhailgavrilenko4300]

Hello.
Problem with instability might be because of electrolytic capacitor have big parasitics, making low frequency pole. I would recommend put MLCC on input and output of topology. Guess 10-47 uF will be enough.

[@erickmone]

Hola Miguel, me gustó mucho tu video, tengo actualmente un proyecto con el mismo driver y la misma basys 3, crees que podrías compartir algo de información conmigo?, honestamente no me han salido mis pruebas con el ir2110. Saludos!!

[@miguelprado7092]

Gracias por ver el vídeo. Mándame un mensaje a [e-mail]

[@erickmone]

@@miguelprado7092 hola Miguel, te mande correo pero me imagino que te llego a spam! Podrías checarlo? Saludos!!

[@HarinathRao-dv6mp]

Can I get code and Circuit diagram ?

[@milariha007]

Hi Miguel, nice work. Do you plan to publish VHDL code?

[@miguelprado7092]

I don't have plans to publish the source, but I you are interested send me an email and I'll share it with you. [e-mail]. Thank you for watching.

[@dimostheniskatsis2006]

Which version of Vivado are you using?

[@miguelprado7092]

Hi, the version I used is the 2020.1. Best regards!

[@64_bharatkhanvilkar31]

Can I get the code ?

[@miguelprado7092]

Of course,, send me an email to [e-mail].

[@RPBCACUEAIIBH]

Fatal: English expected(Title is English) unintelligible gibberish found!