𝐅𝐢𝐱𝐞𝐝 𝐏𝐫𝐢𝐨𝐫𝐢𝐭𝐲 𝐀𝐫𝐛𝐢𝐭𝐞𝐫 | 𝐕𝐞𝐢𝐥𝐨𝐠 𝐃𝐞𝐬𝐢𝐠𝐧, 𝐒𝐢𝐦𝐮𝐥𝐚𝐭𝐢𝐨𝐧 & 𝐒𝐲𝐧𝐭𝐡𝐞𝐬𝐢𝐬 | 100 𝐑𝐓𝐋 𝐏𝐫𝐨𝐣𝐞𝐜𝐭𝐬 |

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  • Опубліковано 29 січ 2025

КОМЕНТАРІ • 7

  • @vlsiexcellence
    @vlsiexcellence  2 роки тому

    𝐇𝐞𝐫𝐞 𝐢𝐬 𝐭𝐡𝐞 𝐏𝐫𝐨𝐣𝐞𝐜𝐭 𝐒𝐨𝐮𝐫𝐜𝐞 𝐂𝐨𝐝𝐞 𝐆𝐢𝐭𝐇𝐮𝐛 𝐋𝐢𝐧𝐤: github.com/vlsiexcellence/Digital-ASIC-Design-Projects-/tree/main/Fixed%20Priority%20Arbiter

  • @khanmubashir8652
    @khanmubashir8652 2 роки тому +1

    Very nice lecture sir
    Sir want a career in vlsi, how should I proceed, I am very much confused. Kindly guide me, how should I start, which training Institute should I join. On what subjects should I focus upon.
    I shall be highly grateful

    • @vlsiexcellence
      @vlsiexcellence  2 роки тому +1

      Hi @Dayis of Allah, Please focus on the Fundamentals for Freshers/Entry Level Jobs.
      For Digital Profiles -> Focus on Digital ELectronics in Deep + VHDL/Verilog Concepts + Solve as many Problems as Possible
      For Analog Profiles -> Focus on Analog Electronics in Deep + VHDL/Verilog Concepts + Solve as many Problems as Possible
      Basic Digital, Analog Concepts should be Clear.
      Thanks !!

    • @khanmubashir8652
      @khanmubashir8652 2 роки тому

      @@vlsiexcellence
      Thank you sir
      Highly grateful to you

  • @muskangautam492
    @muskangautam492 2 роки тому +1

    hey can you please send me the code?

    • @vlsiexcellence
      @vlsiexcellence  2 роки тому +1

      Hi @Muskan, Here is the Project Link: github.com/vlsiexcellence/Digital-ASIC-Design-Projects-/tree/main/Fixed%20Priority%20Arbiter
      Thanks !

    • @muskangautam5808
      @muskangautam5808 2 роки тому

      @@vlsiexcellence Thankyou so much