Floorplanning in VLSI Physical Design

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  • Опубліковано 10 лют 2025

КОМЕНТАРІ • 2

  • @Dragon_Company
    @Dragon_Company 4 місяці тому +1

    Hello my friends. I have encountered the following problem:
    There is a way to fix a Setup Violation called Register Duplication - by duplicating registers, the timing paths can be shortened, reducing the wire and cell propagation delays.
    This can be done in the following ways - Duplication can be done manually in the RTL or automatically by the synthesis and PnR tools.
    I have not found a way to do this in PnR tools (Innovus). Maybe you can tell me?

    • @TechSimplifiedTV
      @TechSimplifiedTV  3 місяці тому

      The problem you are mentioning here , there could be two ways to approach:
      1. Check with your senior/manager who are more experienced than you whether they have faced similar issues , if so you will get the solution within your team
      2. You can open/raise a ticket. all EDA vendors have strong team of application engineers and they are very efficiently trained to solve customer issues. They are the right persons to help you with the tool specific query.
      Thanks for watching the video.