Hi Aryan, thank you for watching. To download the library you must possess a .edu email address. Use this link to register and a download file with several different foundries will be sent to you. www.eda.ncsu.edu/eda_registration.php The rest of the setup (such as copying the files to your Linux account, linking the libraries to your working directory, and editing .cshrc file if necessary) should be provided by your instructor as it may vary from server to server.
Good afternoon, When I am trying to create the instances for the pmos and nmos for the layout, I am getting different layouts for both transistors. Would you happen to know why is that ?
Hi I apologize for the late reply, hope I'm not too late. Can you clarify what you mean by different layout for nmos and pmos, So I can make a better explanation? I'm just going to shoot off a few ideas that I may have at the moment: 1. I'm using TSMC 180nm foundry, if you are using a different foundry(not in the TSMC family), the layout may have different colors for the individual layers but the concept is the same. 2. Nmos and pmos layout are inherently different due to the different layers are used to make them. 3.If the difference is due to sizing and/or different amount of fingers(gates). You can use the property editor(hotkey Q) to change them to the desired measurements.
Greetings, how can we download and add this library(NCSU_TechLib_tsmc02d)?
The instructions were very clear, thank you for the great video
Hi Aryan, thank you for watching.
To download the library you must possess a .edu email address. Use this link to register and a download file with several different foundries will be sent to you.
www.eda.ncsu.edu/eda_registration.php
The rest of the setup (such as copying the files to your Linux account, linking the libraries to your working directory, and editing .cshrc file if necessary) should be provided by your instructor as it may vary from server to server.
Good afternoon, When I am trying to create the instances for the pmos and nmos for the layout, I am getting different layouts for both transistors. Would you happen to know why is that ?
Hi I apologize for the late reply, hope I'm not too late.
Can you clarify what you mean by different layout for nmos and pmos, So I can make a better explanation? I'm just going to shoot off a few ideas that I may have at the moment:
1. I'm using TSMC 180nm foundry, if you are using a different foundry(not in the TSMC family), the layout may have different colors for the individual layers but the concept is the same.
2. Nmos and pmos layout are inherently different due to the different layers are used to make them.
3.If the difference is due to sizing and/or different amount of fingers(gates). You can use the property editor(hotkey Q) to change them to the desired measurements.