Dear Ranveer, you deserve it.. I will consider it as my achievement as well. I appreciate your attitude that you share it with me.. Keep in touch and all the best for your carrier.
@@TechnicalBytes Sir earlier I was in software industry for less than a year then in coaching industry for IITJEE and trained students in Mathematics for 4.5 years and then joined MTech last year and got placed from campus now, I am a fresher in Semiconductor Industry. My job location is noida sir.
sir, then why is behavioural simulation important, if it is not going to similar to the post synthesis results, because it is actually the synthesised netlist that is going to be final product.
Hi Jatin, thanks for initiating this discussion here .. there will not be any latch getting infer from both the codes discussed above. for more clarity on latch generation, I have created a separate video, please go through it and let me know if you still have any doubt. Link: ua-cam.com/video/o-Ws4XmszFI/v-deo.html
@@TechnicalBytes Sir I have watched the video but not able to relate examples given in that with this video. In 2nd case blocking statements are used and o requires value of temp which has not been assigned till now. So previous value of temp will be used and that is possible only through a latch. o = a&b|temp in this previous value of temp will be used this what I am trying to say for 2nd case. If you can please post its synthesis result it will solve all the doubts.
I'm an RTL designer at Intel and I can say that the quality of your videos and interview questions are really relevant and good! Keep it up!
Thank you so much for your encouraging words !!!!!
@@TechnicalBytes can you please make a video on timing regions in verilog? This topic has not been covered anywhere!!
very nice explanation Sir
🎁🎉😇😇😊
Sir I got placed in NxP yesterday, your videos helped a lot technically gaining confidence.
Dear Ranveer, you deserve it.. I will consider it as my achievement as well.
I appreciate your attitude that you share it with me..
Keep in touch and all the best for your carrier.
Ranveer, how many years of experience do you have??
what is your job location?
@@TechnicalBytes Thanks a lot sir
@@TechnicalBytes Sir earlier I was in software industry for less than a year then in coaching industry for IITJEE and trained students in Mathematics for 4.5 years and then joined MTech last year and got placed from campus now, I am a fresher in Semiconductor Industry. My job location is noida sir.
@@ranveerdhawan5187 Congratulations dear !!!!! NXP is a very good company !!!!!
sir, then why is behavioural simulation important, if it is not going to similar to the post synthesis results, because it is actually the synthesised netlist that is going to be final product.
According to me synthesis results of both the codes will be different. In the second code latch will be generated at temp. Please clarify.
Hi Jatin, thanks for initiating this discussion here .. there will not be any latch getting infer from both the codes discussed above. for more clarity on latch generation, I have created a separate video, please go through it and let me know if you still have any doubt. Link:
ua-cam.com/video/o-Ws4XmszFI/v-deo.html
@@TechnicalBytes Sir I have watched the video but not able to relate examples given in that with this video. In 2nd case blocking statements are used and o requires value of temp which has not been assigned till now. So previous value of temp will be used and that is possible only through a latch. o = a&b|temp in this previous value of temp will be used this what I am trying to say for 2nd case. If you can please post its synthesis result it will solve all the doubts.
Thanks for sharing
My pleasure
Thanks 🙏🙏
You’re welcome 😊