System Verilog Constraints And Interview Questions

Поділитися
Вставка
  • Опубліковано 31 жов 2024

КОМЕНТАРІ • 6

  • @narennaren436
    @narennaren436 2 роки тому +2

    Q1. Second solution is faster, as the list of primes is readily available
    Q3. Using post_randomize() would be faster, as addr is not declared as a rand variable
    Q4. bit [31:0] addr;
    rand bit [4:0] pos1, pos2;
    constraint addr_c {
    pos1 != (pos2+1);
    pos2 != (pos1+1);
    }
    function void post_randomize();
    addr = (1

  • @gokulp6878
    @gokulp6878 2 роки тому +1

    your examples are very useful

  • @punithapg4261
    @punithapg4261 2 роки тому

    Pls explain ABT assertion and coverage

  • @SanthoshKumar-tg1nm
    @SanthoshKumar-tg1nm 2 роки тому

    Sir Can you please provide some other constraint assertions and coverage based examples with real time examples in interview point of view

  • @gokulp6878
    @gokulp6878 2 роки тому

    Can you please explain the constraint for axis and ahb protocol based?

  • @meenakshi5362
    @meenakshi5362 Рік тому

    RV-Skills tutorials?