Synchronous Reset Asynchronous Reset in Sequential design with verilog code

[@ExploreElectronicsPlus]

Very Important for the interview! SUBSCRIBE FOR MORE!
0:30 Differences between sync and async reset
2:24 Verilog code

[@varakarri5902]

Awesome explanation sir

[@User--jm5916]

Please make videos on how to crack interviews also, it will help many freshers who are trying to get in VLSI field

[@VSCSMITHAVENKAT]

Could you please explain about giving @negedge clk and @posedgeclk in the testbench for reset