Really excellent video, thank you. This is the first time in over 20 years I've used GALs and I had forgotten everything and I've no idea what software tools I used back then. Your video has got me back up and running with GALs and now is so much potential!!
Microchip currently produces the PAL ATF16v8 & ATF22V10 series of devices. The TL866II Plus will program ATF16V8BQL-15PU devices, I have yet to purchase or use any ATF22V10 devices. The ATF16V8BQL-15PU work great for address decoding, it can reduce complex decoding to one IC over half a dozen 74HC IC’s.
Thank you very much, your explanations helped me to understand most of the logic, functions and programming for gals. Greeting from germany , stay retro ;).
These early PAL/GAL (Lattice) programmable gate arrays are from my heyday as a design engineer at Baker Electronics. I got out of electronic design just as things were beginning to use Altera and Xilinx FPGA/CPLDs. Nice walk down memory lane. Thank you for showing us sir. Fred
At the demonstration of the Johnson counter I half expected it to turn backwards and that a montonic voice would say "By your command" or that it would shout out the name Michael :P Thanks for this informative video. I find WinCUPL a pain to work with, but fortunately I found some alternatives that may not be ideal, but that work for what I currently use these devices for.
Great video - I have been wanting to experiment with GALs to do some address decoding on some homebrew 8 bit computers and had no idea where to start.. This was a great help!
All the info I should of know but didn't and still had to repair just understanding function. Definition of a "parts swapper", and still got paid. Thanks for the look.
I took a course in early 90s which we would wire the gates/latches/FF using a Windows 3 GUI program. I think it was a part of Spice software. Then we learned about Verlog and VHDL to write code. Because I was an EE, I liked the wiring program. I remember it would take about 30min to complie several software.
I used to use PALs at one company in the mid-1980s or so. Fun ! CPLDs and Silegos today. I hope they keep making them> I didn't know anyone still made 22V10s ! Kinda expensive for that old of parts though
Microchip (Atmel) still makes 7.5ns fast CPLD like the ATF750C in 24 pin DIP or 28 pin PLCC that can handle 5V. at mouser, they are going for 7€ a piece.
Thanks: I was curious how GALs differed from PALs - so they basically added the option of flip-flops on the outputs, and the ability to loop outputs back as inputs. They're still just a big LUT (Look-Up Table) though, with the AND array forming a compact decoder, and the OR array as the table. An FPGA consists of many LUTs, all connected through a bus of sorts, with the inputs & outputs connected separately to the bus. Traditional wisdom holds that all LUTs marry with FFs (Flip-Flops), but I've found it more efficient to connect the FFs separately, and you can always have part of a LUT configured as a FF, by feeding it back to itself. (The simplest illustration of this, is configuring an OR gate into a LUT, then feeding the output back into one of the inputs. This is also a good test of how good your gates are, as power and data should be separate.) This has made me think though, if I can make some of my decoders compact, ie allowing a large number of inputs, where only a relatively-small combination of outputs needs to be valid: If this would save space over having a huge decoder. If the AND array replacing it had to be a similar size however, there would be no advantage - this is something I need to work through.
Hello nice explaining on the gal pal architecture but on minute 23 you say that the pin one is reserved only for clock this is wrong pin one is the clock input but if you do not need clock you can program it as a an input
Great video. Do you have some where you keep your example code? I have just got the T48 programmer and some 22v10 for Christmas, and would like to 'work along' with you.
I have got the hang of this now, snap shotting the screen and printing them. I have now replicated what you have shown here, and done my own clock divider for my video project. Thanks again IMSAI. 🙂 Love your stuff.
Very interesting! I've programmed these with ".jed" files designed by others (when building projects that they designed), but I've never written the logic for one, myself. This makes it sound quite approachable. Really, it reminds me of all those truth tables I had to fill out and analyze in one of my very early classes for computer science. I didn't think that they were technically obsolete chips, though; doesn't some company produce the Lattice parts now, after buying Lattice? I'm pretty sure that I've bought new ones in the last few years from Mouser or Digi-Key. 🤔
What is the small PCB with the LEDs on it? Is it just a PCB with LEDs for use on a solderless breadboard? If you bought it somewhere, could you provid a link?
I am a BSCS student, i have studied about the introduction of GAL gate, can you upload the video on How to program & implement some SOP expression on GAL PLDs.❤ Regards,
I know this is off topic, but I was working on an old Tandy TRS-80 Model II, and the 12 volt line is at 9v with nothing connected What would cause a supply to drop voltage? I don't know many people I could ask.
@@IMSAIGuy obviously, help only if you want too, but the schematic is on page 117 of this manual github.com/pski/model2archive/blob/master/Hardware/Model_II_Technical_Reference_Manual.pdf
D8 could be half way dead loading it down. or as usual one or more capacitors are dead and you just checked with a voltmeter and not a scope. I would put a scope on it and see if you have massive amounts of ripple. My bester guess is bad caps
This is a great introduction, but -- and maybe I'm missing something here -- the schematic of the synchronous counter at 14:32 doesn't actually work, and doesn't match the logic that you wrote in WinCUPL (which can be seen at 26:22). The CUPL code does work (as you demonstrated!), but the schematic diagram can't possibly be what the compiler actually generates (not quibbling with the use of a higher-level language like CUPL here... but obviously the compiler is doing some real work since the 22V10 doesn't support XOR in the way that's being used in the code). Initial state is Q1=0, Q2=0, Q3=0. After the first clock pulse, Q1=1, Q2=0, Q3=0, and therefore FF2.D=1... so far so good... now, strobe the clock again and Q1=0, Q2=1, Q3=0. Now here's the problem: because Q1=0, FF2.D=0 (heck, /Q2=0, which also ensures that FF2.D=0). So, if you strobe the clock again, Q1 correctly becomes 1, but Q2 goes back to 0, and now on each clock pulse they just ping-pong. I haven't taken a look at the low-level fuse map that WinCUPL actually generates for the code in the example so I can't say what it actually puts into the device, but in addition to toggling a given bit if all of its trailing digits are 1, you also need to preserve a digit's 1 if any of its trailing bits are 0. The easiest way to do that is to just AND the digit with the inverse of each of its trailing digits individually, and then OR the whole thing together. Anyway, I just wanted to point this out in case anyone else is using something other than WinCUPL to write code for the device (there's a couple of open-source tools -- GALasm and Galette) that only exposes the sum-of-products that the GAL uses internally, they shouldn't just transcribe the schematic!
@@IMSAIGuy that article is rather inconsistent. Please refer to corresponding Wikipedia article: en.wikipedia.org/wiki/Flip-flop_(electronics)#D_flip-flop A D flip-flop can be obtained with two gated D latches connected in series.
@@IMSAIGuy 7475 has transparent latches (another name for gated D latch). The TI datasheet says: "Information present at a data (D) input is transferred to the Q output when the enable (C) is high and the Q output will follow the data input as long as the enable remains high." Now take a look at the 7474 datasheet.
So "the AND:s over here..." Are you saying that all horizontal connections in the grid forms an AND gate? You are very unclear on HOW these AND gates are formed.
at 10:08 : your definition of FLIP-FLOP is wrong. A flip-flop is simply a clocked latch or if you prefere, a single bit register. You have transformed a D-Flip Flop in a T-Flip flop.
I do call it a D type latch in the video also. the term flip flop is due to my old age. if you look at old TTL 7474 parts. the datasheet says they are D-type positive edge triggered flip-flops. people of my age learned that way. today it is more accurate to call them latches. the TTL 7475 is called a latch on its datasheet. So TI just taught us that way.
@@IMSAIGuy the problem is the word "latch" used describing a flip-flop. A latch is a device that *don't have* the clock. Also the one you called a D- flip flop is a toggle flip flop (T-flip flop)
The FPGA is sooo much easier. Forget the programming and just enter a graphic of the circuit using off the shelf parts. Connect 3 wires to the computer's serial port and Bob's your uncle.
Not really. FPGA typically require external ROMs for programming on start-up, and rarely (if ever) run at 5V or even have 5V tolerant pins. So in addition to the FPGA, you need the external ROM and voltage level converters (either standard MOSFETs or TTL chips that can run at lower voltages.) A GAL runs native at 5V and requires no start up time at all, even if they are significantly more limited in functionality.
I really wanted to enjoy and learn from this video. Sadly with your fingers mostly obscuring what you are pointing to and not understanding which things are things and which are not I was sadly frustrated. May I suggest that you watch your video with a critical eye and ear. Please take this as constructive criticism.
Really excellent video, thank you. This is the first time in over 20 years I've used GALs and I had forgotten everything and I've no idea what software tools I used back then. Your video has got me back up and running with GALs and now is so much potential!!
Excellent
Microchip currently produces the PAL ATF16v8 & ATF22V10 series of devices. The TL866II Plus will program ATF16V8BQL-15PU devices, I have yet to purchase or use any ATF22V10 devices. The ATF16V8BQL-15PU work great for address decoding, it can reduce complex decoding to one IC over half a dozen 74HC IC’s.
Thank you very much, your explanations helped me to understand most of the logic, functions and programming for gals. Greeting from germany , stay retro ;).
These early PAL/GAL (Lattice) programmable gate arrays are from my heyday as a design engineer at Baker Electronics. I got out of electronic design just as things were beginning to use Altera and Xilinx FPGA/CPLDs. Nice walk down memory lane. Thank you for showing us sir. Fred
Thanks for that, it took me right back to the early 80s :~D
Microchip still produces that - ATF22V10, ATF16V8, you name it :)
Yes, but good luck getting them in the current shortage!
Thanks for making this video, I really appreciate it. There don't seem to be a huge number of videos about these days talking about GALs. :D
At the demonstration of the Johnson counter I half expected it to turn backwards and that a montonic voice would say "By your command" or that it would shout out the name Michael :P
Thanks for this informative video. I find WinCUPL a pain to work with, but fortunately I found some alternatives that may not be ideal, but that work for what I currently use these devices for.
Great video - I have been wanting to experiment with GALs to do some address decoding on some homebrew 8 bit computers and had no idea where to start.. This was a great help!
Glad I could help!
Thank you! Now I am imagining self-modifying fabrics of these things. Someone must have tried this.
All the info I should of know but didn't and still had to repair just understanding function. Definition of a "parts swapper", and still got paid. Thanks for the look.
I took a course in early 90s which we would wire the gates/latches/FF using a Windows 3 GUI program. I think it was a part of Spice software. Then we learned about Verlog and VHDL to write code. Because I was an EE, I liked the wiring program. I remember it would take about 30min to complie several software.
Fascinating. I have some GALs coming from China. I may give it a try when they arrive.
I used to use PALs at one company in the mid-1980s or so. Fun ! CPLDs and Silegos today. I hope they keep making them>
I didn't know anyone still made 22V10s ! Kinda expensive for that old of parts though
Happy times spent with PALASM hunched over a programmer!
Glad u made this i have a few òf the gal18v10b ic thanks
I now have a better understanding of how it works :)
Thanks as always..
Microchip (Atmel) still makes 7.5ns fast CPLD like the ATF750C in 24 pin DIP or 28 pin PLCC that can handle 5V.
at mouser, they are going for 7€ a piece.
Thanks: I was curious how GALs differed from PALs - so they basically added the option of flip-flops on the outputs, and the ability to loop outputs back as inputs.
They're still just a big LUT (Look-Up Table) though, with the AND array forming a compact decoder, and the OR array as the table.
An FPGA consists of many LUTs, all connected through a bus of sorts, with the inputs & outputs connected separately to the bus. Traditional wisdom holds that all LUTs marry with FFs (Flip-Flops), but I've found it more efficient to connect the FFs separately, and you can always have part of a LUT configured as a FF, by feeding it back to itself. (The simplest illustration of this, is configuring an OR gate into a LUT, then feeding the output back into one of the inputs. This is also a good test of how good your gates are, as power and data should be separate.)
This has made me think though, if I can make some of my decoders compact, ie allowing a large number of inputs, where only a relatively-small combination of outputs needs to be valid: If this would save space over having a huge decoder. If the AND array replacing it had to be a similar size however, there would be no advantage - this is something I need to work through.
Thanks again...
Very handy if you want to build a hardware DES cypher module
Hello nice explaining on the gal pal architecture but on minute 23 you say that the pin one is reserved only for clock this is wrong pin one is the clock input but if you do not need clock you can program it as a an input
Great video. Do you have some where you keep your example code? I have just got the T48 programmer and some 22v10 for Christmas, and would like to 'work along' with you.
I have got the hang of this now, snap shotting the screen and printing them. I have now replicated what you have shown here, and done my own clock divider for my video project. Thanks again IMSAI. 🙂 Love your stuff.
Very interesting! I've programmed these with ".jed" files designed by others (when building projects that they designed), but I've never written the logic for one, myself. This makes it sound quite approachable. Really, it reminds me of all those truth tables I had to fill out and analyze in one of my very early classes for computer science.
I didn't think that they were technically obsolete chips, though; doesn't some company produce the Lattice parts now, after buying Lattice? I'm pretty sure that I've bought new ones in the last few years from Mouser or Digi-Key. 🤔
Yeah Today we Have FPGA's field programable gate arrays!
What is the small PCB with the LEDs on it?
Is it just a PCB with LEDs for use on a solderless breadboard?
If you bought it somewhere, could you provid a link?
It is my own design
thanks for the helpful video.
Is it possible to copy the chip with protection?
no way to read it
I am a BSCS student, i have studied about the introduction of GAL gate, can you upload the video on How to program & implement some SOP expression on GAL PLDs.❤
Regards,
what is SOP
I know this is off topic, but I was working on an old Tandy TRS-80 Model II, and the 12 volt line is at 9v with nothing connected
What would cause a supply to drop voltage? I don't know many people I could ask.
I would need to see the schematic
@@IMSAIGuy obviously, help only if you want too, but the schematic is on page 117 of this manual github.com/pski/model2archive/blob/master/Hardware/Model_II_Technical_Reference_Manual.pdf
@@computeraidedworld1148 OK, If I had to guess D5 or D6 is dead. it is only rectifying half and not full.
D8 could be half way dead loading it down. or as usual one or more capacitors are dead and you just checked with a voltmeter and not a scope. I would put a scope on it and see if you have massive amounts of ripple. My bester guess is bad caps
if you don't have a scope, measure the AC voltage, It should be 0, it should only have DC
Interesting. I havent done this in probably 25 years. You didnt show the programming hardware. What programmer is it?
in the description
This is a great introduction, but -- and maybe I'm missing something here -- the schematic of the synchronous counter at 14:32 doesn't actually work, and doesn't match the logic that you wrote in WinCUPL (which can be seen at 26:22). The CUPL code does work (as you demonstrated!), but the schematic diagram can't possibly be what the compiler actually generates (not quibbling with the use of a higher-level language like CUPL here... but obviously the compiler is doing some real work since the 22V10 doesn't support XOR in the way that's being used in the code). Initial state is Q1=0, Q2=0, Q3=0. After the first clock pulse, Q1=1, Q2=0, Q3=0, and therefore FF2.D=1... so far so good... now, strobe the clock again and Q1=0, Q2=1, Q3=0. Now here's the problem: because Q1=0, FF2.D=0 (heck, /Q2=0, which also ensures that FF2.D=0). So, if you strobe the clock again, Q1 correctly becomes 1, but Q2 goes back to 0, and now on each clock pulse they just ping-pong.
I haven't taken a look at the low-level fuse map that WinCUPL actually generates for the code in the example so I can't say what it actually puts into the device, but in addition to toggling a given bit if all of its trailing digits are 1, you also need to preserve a digit's 1 if any of its trailing bits are 0. The easiest way to do that is to just AND the digit with the inverse of each of its trailing digits individually, and then OR the whole thing together.
Anyway, I just wanted to point this out in case anyone else is using something other than WinCUPL to write code for the device (there's a couple of open-source tools -- GALasm and Galette) that only exposes the sum-of-products that the GAL uses internally, they shouldn't just transcribe the schematic!
Atmel still makes them. about $1 on mouser
10:07 that's a D flip-flop, not a D latch.
A "D latch" would have an "E" input for gating the "D" signal.
You probably meant T flip-flop.
www.electrical4u.com/d-flip-flop-or-d-latch/#:~:text=A%20D%20Flip%20Flop%20(also%20known,as%20a%20basic%20memory%20cell.
@@IMSAIGuy that article is rather inconsistent. Please refer to corresponding Wikipedia article: en.wikipedia.org/wiki/Flip-flop_(electronics)#D_flip-flop
A D flip-flop can be obtained with two gated D latches connected in series.
@@bit2shift We always called them latches, gated latches is something else. the D input is latched on a positive clock edge.
look at the 7475 datasheet
@@IMSAIGuy 7475 has transparent latches (another name for gated D latch).
The TI datasheet says: "Information present at a data (D) input is transferred to the Q output when the enable (C) is high and the Q output will follow the data input as long as the enable remains high."
Now take a look at the 7474 datasheet.
So "the AND:s over here..." Are you saying that all horizontal connections in the grid forms an AND gate? You are very unclear on HOW these AND gates are formed.
at 10:08 : your definition of FLIP-FLOP is wrong. A flip-flop is simply a clocked latch or if you prefere, a single bit register. You have transformed a D-Flip Flop in a T-Flip flop.
I do call it a D type latch in the video also. the term flip flop is due to my old age. if you look at old TTL 7474 parts. the datasheet says they are D-type positive edge triggered flip-flops. people of my age learned that way. today it is more accurate to call them latches. the TTL 7475 is called a latch on its datasheet. So TI just taught us that way.
@@IMSAIGuy the problem is the word "latch" used describing a flip-flop. A latch is a device that *don't have* the clock. Also the one you called a D- flip flop is a toggle flip flop (T-flip flop)
The FPGA is sooo much easier. Forget the programming and just enter a graphic of the circuit using off the shelf parts. Connect 3 wires to the computer's serial port and Bob's your uncle.
Not really. FPGA typically require external ROMs for programming on start-up, and rarely (if ever) run at 5V or even have 5V tolerant pins. So in addition to the FPGA, you need the external ROM and voltage level converters (either standard MOSFETs or TTL chips that can run at lower voltages.) A GAL runs native at 5V and requires no start up time at all, even if they are significantly more limited in functionality.
I really wanted to enjoy and learn from this video. Sadly with your fingers mostly obscuring what you are pointing to and not understanding which things are things and which are not I was sadly frustrated. May I suggest that you watch your video with a critical eye and ear. Please take this as constructive criticism.