CPU? GPU? This new ARM chip is BOTH
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- Опубліковано 3 бер 2020
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Sources & Further Reading:
• "Opening Address: From...
• Striving towards high-...
• A64fx and Fugaku - A G...
www.titech.ac.jp/english/grad...
www.fujitsu.com/downloads/SUP...
www.fujitsu.com/downloads/SUP...
www.fujitsu.com/jp/solutions/...
Some footage from Charbax:
• Fujitsu A64FX Post-K S...
• Fujitsu at CEATEC 2019...
• Fujitsu Post-K ARM Sup...
- Videos from the AMD official UA-cam channel were used for illustrative purpose, all copyrights belong to the respective owners, used here under Fair Use.
- Videos from the Intel official UA-cam channel were used for illustrative purpose, all copyrights belong to the respective owners, used here under Fair Use.
- Videos from the NVidia official UA-cam channel were used for illustrative purpose, all copyrights belong to the respective owners, used here under Fair Use.
- A few seconds from several other sources on youtube (*including other youtubers*) are used with a transformative nature, for educational and illustrative purposes. If you haven't been credited please CONTACT ME directly and I will credit your work. Thanks!!
#A64FX #FUGAKU #FUJITSU - Наука та технологія
RIP SATORU IWATA.
A BRILLIANT AND UNIQUE MIND.
His father never wanted him to pursue a games career.
There's only one video that comes to my mind at this point.
ua-cam.com/video/j2dxX5DIEMQ/v-deo.html
R.I.P. to both.
Intel is better
And I'm glad he didn't listen.
@@masternobody1896 intel is nr.2.
Nice Haiku
A64FX.....Why have I heard that name before?
Oh yeah! Athlon 64 FX!
Yeah, tha name remind´s me that too XDD
So thats where the deja vu feeling came from
What goes round...
I knew I'd seen that somewhere before but I couldn't put my finger on it ! Thanks for the reminder ! :)
FX you...
This video sounds more like a nonfiction crime tvshow than something about processors.
can u share us ur pic?
You make me laugh but at the same time I'm annoyed. This dude has a wealth of knowledge and insights, but he's HORRIBLE to listen to.
Dedicated my life's 20 MINUTES.. Worth it as always..
Absolutely!
Only dedicated 10 minutes. x2 speed is great.
20:36 actually for me..cause I wanted to see my name on the Credits... 🤣😝
Always guarantee when you watch a (Jim) #AdoredTV video ❎
@@johnnyxp64 Being a Coreteks patreon means having big pp
17:28 sure, streaming today data would be instant with tomorrows technology, but what about tomorrows data? The extinction of load times is far away. More powerful computers? That will just be an excuse to use more detailed textures :'D
There will be a soft ceiling for textures butI think it won't be a limitation more a practical one. It'll be a similar argument to the difference between 8K and 4K. How much detail can you see before it's just FOMO.
loading nowadays is no longer limited by file size, it is limited by bad code. NVMe SSDs do many GiB/s, no game asset needs more than the blink of an eye to load. Sadly, developers have some of the fastest possible hardware available (especially in big-budget games and programs), so they have no need to optimize. Running the same code on an average PC then makes it unusable.
The biggest issue is poor telecoms infrastructure. Even in the UK it varies massively in speed, they're already trying to save cost and not put in full fibre.
@jayViant Talking of holograms:
ua-cam.com/video/V7V05T4DhrU/v-deo.html
@@Mil-Keeway compression and bad structuring of data makes for terrible load times rven on high end NVMes. Games before the next get werent optimized for this, maybe except star citizen and arkham knight.
Can't imagine a japanese chip without TOFU interface
iExplorer has SHAKRA engine (as shown in TaskMgr)
and if it was coded in Germany it would have a SAUSAGE Cache pipe... LOL
@@glasser2819 No, it would have a Bierfass (beer jar) pipeline ;) I am german, I should know. ^.^
The driver of AE86 was a tofu delivery man
SUSHI coming up next.
They make the Best capitors .
So,, ARM, AMD and Fujitsu teamed up for a super APU, that's in some ways more epic then EYPC..., I will call this colab FARMeD!
Proof?
@@absoluterainbow it was a tongue in cheek summery of this video and an pun at the end
Thank you for doing what you're. I learn a lot from your videos.
7:55 Not quite. Supercomputing applications actually have limits to their parallelism. There is also a need for heavy communication traffic between cores. Hence the fast interconnect, which is a major component of the build cost of a super.
For an example of a massively parallel application which doesn’t need such heavy interprocessor communication, consider rendering a 3D animation. The renderfarms that are deployed for such an application are somewhat cheaper than supercomputers.
8:53 That doesn’t make sense. “Teraflops” is a unit of computation (“flops” = “floating-point operations per second”), not of data transfer. Data transfer rates would be measured in units of bits or bytes per second.
Yeah, A64FX has 1TB/s theoretical bandwidth and 840GB/s of actual bandwidth.
What you describe sounds like a modern version of the PS3's cell chip.
Kind of, yes! The PS3 used several DSP-like processors connected onto a ring bus - except that rings, as well as other pure bus like topologies, while being the simplest way to interconnect multiple regions on a chip have several inherent limits which restrains this kind of topology to a limited amount of locally adjacent cells which is why the kind of processor presented here not only has one ring, but a hierachy of rings topology:
See this paper as an example for examining & describing different hierachical ring topoligy variants as on-chip interconnection networks, also called NoC = "network on chip"
"Design and Evaluation of Hierarchical Rings
with Deflection Routing": pages.cs.wisc.edu/~yxy/pubs/hring.pdf
This has been a hot reseach topic in hp & scientific computer engineering for several years now.
Another really old, formerly rejected but increasingly interesting & related research topic is "computing-in-memory", also "processing-in-memory" or "near memory processing" because the costs to transfer data between processing units & memory is, as mentioned in this video, increasingly becoming a limiting factor, see
"Computing In-Memory, Revisited": ieeexplore.ieee.org/document/8416393 but also semiengineering.com/in-memory-vs-near-memory-computing/
& while the recent emergence of array processors like Googles tensor cores & other forms of neuromorphic processing units is clearly at least partly due to that, this problem isn't limited to applications using AI but applies to a much broader category of problems - the "bandwidth wall" is a thing.
@@FrankHarwald One of the biggest headaches of working with the cell BB was the relatively tiny amounts of accessable memory each SPU had (256kb IIRC). This meant you couldn't use a lot of general purpose algorithms and instead had to modify them to be streamable with high locality of reference - for some algorithms it just isn't possible to optimise in such a way.
@@SerBallister indeed, but modifying algorithms so that they run with a high amount of locality is something that you'll have to do for all data intensive algorithms anyway - no matter how much of it is done automatically, profiler-assisted or by hand - regardless of what the underlying architecture is because while all shared memory architectures will start hitting the bandwidth wall at some point, distributed memory architectures will be the only way to circumvent these limitations. & yes, this also means that algorithm that access a lot of memory from the same chunk in a purely serial way will either have to be modified to access data in parallel from multiple chunks (if possible) or remain bandwidth limited (if this is acceptable or if the algorithm is inherently serial).
@@FrankHarwald You should aim for that yeah. The SPU local memory presented an addressing barrier instead of a cache miss like on a multicores, all data has to be present in that block. Take a ps3 game for example. Some systems like physics and pathfinding can be hard to compress your game world in 256kb, the PPU had to work on that stuff and you then had the headache of pipelining the output of that into the SPU (e.g. animation) if you want to avoid stalls. Interesting chip but can be hard work, task scheduling and synchronisation is also not straight forward. I would prefer working with modern desktop multicores with shared memory.
of course it is
If you haven't already, you may want to look into RISC-V's upcoming Vector extension. It does all that SVE does, but better.
Better how?
@@Toothily There are a couple of independent things. For one thing, there's no architectural upper limit to the number of vector lanes. Another thing is that the dynamic configuration of the vector registers allows better utilization of the register file (for example, if only a couple of vector registers are used, they can subsume the register storage of the other registers to get much, much wider vectors). Also, while that part of the specification is still a bit up in the air, there is an aim to provide for polymorphic instructions based on said dynamic configurations, which means that it's far easier for it to adopt new data types with very small architectural changes. They also aim to provide not only 1D vector operations, but even 2D or 3D matrix operations, which could provide functionality similar to eg. nVidia's tensor cores, except in a more modular fashion.
There are more examples too, but I think this post is running long enough as it is. I recommend reading the specification.
@@chuuni6924 that sounds really cool spec wise, but do they have working silicon yet?
@@Toothily The spec isn't even finalized yet, so no, there's definitely no silicon yet. However, the Hwacha research project is being carried out in parallel and I know there's a very strong connection between it and RV-V, and I believe they have working silicon in some sense of the word. It's a research project rather than a product, however, so not in the ordinary sense of the word.
Really wanted to know, what you guys think/opinion about this computer compared to nvidia dgx a100?? Does it has equal performance or something? I really excited to know this. Thx :)
I once heard that HAL got its name by grabbing IBM's and ticking the characters because they saw themselves as "one step ahead of IBM". Seeing this, I truly believe it.
ticking them back, not forwards
Woot !! Coreteks is back, feels like its been forever...
Don't you just love their Masonic logo? The honeycomb hexagon also known as the Cube, a reference to Saturn and the system we live in. Just so happens to also be in the beehive colours.
your video presentations are so well done. I always look forward to watching them! such an interesting product. thank you for covering this!
Congratulations on 100.000 subscribers !! I love your videos and i came a long way in computer khnowlage because of you , i hope you have a great year ! Love you from EU Si ♥️😊
Those chips are cool and all, but did you see THIS? 18:04 That truck has FOUR WHEEL STEERING, now THAT is innovation
They have been on the roads for years...
there is also all wheel steering at the wheels at the back too, look at this tatra video ua-cam.com/video/U-ujpvOeydk/v-deo.html
lots of 3-axle garbage trucks in europe have frontmost and rearmost steering, pivoting around the middle axle basically.
@@onebreh pog realy ?
You call that innovation? Get back to me after you google 'Spork'
Loved this video so much, watched it twice in a row.
The comparison with the duel intel xeons is a little silly now that they have already been blown out of the water with eypc.. still an interesting CPU tho..
I think people are going to get surprised when AMD announces Milan this year.
Also, the Frontier 1.5 exaFLOPS supercomputer will use a CPU chiplet + 4 GPU chiplets + memory in the same AMD chip.
The question is, what is more EPYC?
I agree. With how many problems Intel has been having for the last 4-5 years stagnating them on 14nm, comparing anything besides other x86 CPUs to Intel feels disingenuous.
If they compared this ARM chip to the actual current x86 performance leader (a 2U Epyc Rome server with 128 cores) it would be beaten by at least 2-3X. Maybe performance per watt would be better on the ARM chip, but the performance density would almost definitively be unbeaten.
@@BrianCroweAcolyte This isn't the first time ARM was expected to be dominate. It happened int he 90's as well. In fact Microsoft made Windows NT compatible with ARM back then. There was big promise that RiSC cpus would take over the world. Well, that didnt happen, and i still dont think it will happen today or in the future.
@@aminorityofone ARM will probably continue to dominate the market where chips are designed for purpose (unless RISC-V takes that market), mostly because x86 isn't licensed to anyone new.
I like that progress bar ads
Thank you for yet more fantastic content!
I read you make (at least some?) of your own background music
(WOW!)
You're finally back. Thanks again for the amazing work.
Awesome video bud, some very interesting info there. Thank you
17:01 Reseat that RAM!
Kenta Aoki lol I noticed that too
Oof
Man your videos always inspire me to read more computer architecture .
I have computer architecture as a subject in my bachelor's and i don't like it but your videos always inspire me to read it more.
Thank you again for your insight, and all the info.
Finally the first video since I subscribed! I watched all your previous videos lol
Great Video! Thanks!
Simply mind blown! Wow!
Thank you, amazingly educational video!!!
7:15 Finally the memory bottleneck is being some what addressed.
Great video as always! Def a top fav tech channel! Keep em coming! ❤️👌🔥
And ARM already has announced the SVE2 extension which is a replacement for their NEON instruction set (for home/multimedia usage instead of SVE1 which is tuned for HPC workloads). Interesting times are ahead and can't wait for ARM storming the PC desktop...
"The future is Fusion", the slogan was just 12 years ahead of the technology
Awesome video man! Ty for the great content
I am a fan. Good content man. Thanks for your research and sharing the knowledge.
I am no engineer in any shape, but with Coreteks videos I am getting such a digestible form of explanation that teaches me, even thaw i am 37yo) Thank you so much!
37 is not too late. God willing you will be learning well past 37 and even at 73.
I'm 101 years old and still learning!
@@Seskoi in base ten?
@@IARRCSim they opened schools on Mars - finally)
@@Seskoi
I'm 1,009,843,000 seconds old and I push myself every nanosecond to learn more and more
5:36 Actually, the plural of “die” is “dice”.
Yes, those dice. As in the phrase “the die is cast”, which means instead of throwing several dice, you have thrown just one, and must stand by whatever it shows.
The "die is cast" comes from the middle high German/English Gutenberg printing. The printed page came from a single die cast, which is why it was slow and expensive (though cheaper than the Monks drawing each page by hand). This allowed Bibles to be printed, helped people learn how to read, and bring education to the people.
@@ehp3189 That can’t have been right. Guternberg’s innovation was the invention of movable-type printing, as in having separate pieces for each letter that were assembled to make up a page. Printing an entire page from a single block was a technique that had been invented by the Chinese centuries earlier.
@@lawrencedoliveiro9104 Granted, but the expression goes more towards the assembled type set being cast together in a block and any changes to that during a printing run were not to be allowed. It was difficult enough that breaking apart the group and then reassembling it for one letter change was more expensive than it was worth. At least that is my understanding. I liked philologogy in college but they only offered one class ...
I stumbled upon your channel when viewing your interview of Jon Masters and have binge watched 3 episodes losing sleep. Kudos. I am learning a lot! Thank you. I havent binge watched in a long time.
Glad to see your videos again!
Thank you for your educated entertaining info!
Impressive as always, sir. Thank you.
Damn this video had aged well... so good. Wish more videos like this were made and popular on UA-cam.
Fascinating documentary, you clearly put a lot of work into this
Amazing and interesting. Thanks for the video
Nice vid dude. Any idea on power figures between V100 and the ARM chip?
Thanks for the fascinating video!
When are we going to see desktop CPUs with 3D stacked memory and realistically how much memory is it going to have? I can't see 32GB of system memory fitting on a normal desktop die but maybe I'm wrong. Or will it just be a small amount of on-die memory to be used like an extra cache layer but you still have your normal DDR system memory?
Also, I can't be my head around heat dissipation in this new 3D stacking future. Given heat is the biggest issue in 2D chips and atm we can cool directly on to the only layer there then 3D stacking just doesn't sound like it's going to work on anything other than ultra low powered chips to me.
I guess you could try to have some kind of micro coolant channels flowing between layers or maybe thin sheets of graphene but this will be expensive and complex to integrate plus If you have to go from CPU's running at 5GHz to them running at 1.8GHz then I can't see the benefits of closer system memory being enough to overcome this inherent drawback.
True story. Yes we will see 3D stacked CPUs with some kind of RAM on them. (My guess is 2023). We've seen GPUs already that have large HBM stacks "on-chip", and we will see them integrated to even more "on-die". Since Intel has invented its "Foveros" tech to avoid the Interposer layer and TSV's. It does seem like the RAM packages would be almost as large in die size as the CPU. (judging back to the HBM GPUs). Also, Remember the 128MB EDRAM L4 cache on the integrated GPU of Broadwell 5775C (2015)? Granted it was for the iGPU, but that was an early proof of concept of CPU+RAM, and took up a very large real estate of that chip. It wasnt market friendly, the proportions and cost were all wrong for mass-marketability, but it was interesting to say the least. Right now its probably easy enough to add a stack of 1 or 2 modern 16Gigabit DRAM die (=2 or 4 Giga BYTES), thats just my speculation.
They've also been researching that micro-coolant-channel science as a real possibility lately. And you're right, the heat in the 3D stacks is the main issue. Everyones trying to stack the best way possible, its just a question of how.
Then again, besides the real science of it, theres commercial viability concerns. The currently long-standing seperation between the CPU and RAM markets, means we get good prices on both. RAM as a commodity as we know it would be at risk if the 2 main CPU makers are integrating it onto a CPU. The move away from "memory modules" we all know and love would be too hard to do. Plus, think Apple laptops and planned obsolescence; they already solder the RAM on the motherboard, I'm sure they'd love it soldered right on the CPU. So we can buy $1000 CPU+RAM combo-chips and throw them away in 3 years when Chrome starts using 128GB of ram. I'd be more convinced if it was a small L4 cache idea, and leave system RAM alone.
he does NOT want to mentiion the downfalls , we can barely keep heat off our current cpus and gpus, so 3d stacked? nah the amount of power needed, and cost to switch a billions of severs ,no happening
Having things as simple as the video suggests would be a dream. Unfortunately, we'll keep having multiple levels of memory like we always have for over 50 years and different speeds, capacity, and prices per capacity for each. That means any software developers eager for better performance will need to continue optimizing for that complicated layout and be mindful of how it all works. Drastically more L3 cache would be great but there will always be demand for different capacities that strike a different balance on speed, price per unit of capacity, and capacity. RAM Drives introduced at ua-cam.com/video/6pp_krChw_A/v-deo.html do a great job of explaining some of the tradeoffs between speed, price, and others between SSD-like memory vs RAM.
When it hits consumer it will probably have HBM3 memory with up to 64gb on die. Since you won't need ram and GPU, PCs will become micro form factor, imagine how many sockets for these monsters can u fit on standart ATX motherboard without chipset, pci-e slots, etc? :)) and u just need to watercool that bitch with AIO or custom loop. U can add for example 12tflops another chip when u run out of resources or add smaller performance one and they will stack together :) and then add most powerfull one when u get money :) and continue your life with 3 cpus and add one more in 5-6 years :)
@@johannajohnson310
I'm inclined to agree, there's only so much efficiency you can squeeze out of silicon no matter how it's designed.
Hey, I was about to take a nap. ;D Thanks for the content!
When I heard "CPU and GPU" I was thinking AVX turned to 11
Thanks for another fantastic video!
Your channel is a gold mind for computer engineers I really like your analysis and getting into details more then other channels do.
In other note, I really want to see a video about RISC V and its future in personal computing and IoT I'm currently learning RISC V assembly and planning on building a small RISC V CPU on a FPGA but I'm very curious about its future and if it worth the effort.
Was worrying you disappeared. Glad we got a new video.
If the utilise the newest HBM version instead of traditional DRAM for Cache it would vastly increase its processing speed and reliability but also dramatically increase production costs
Very interesting video and I believe you are spot on in your predictions.
I've been seeing this coming for years now.
Very excited for the video on neuroscience and computing!
I've been waiting to see hbm used on a processor! Awesome job, it was exactly what I was predicting. As always great video Coreteks.
And a few months later we see many design choices here (especially the on-chip memory) in Apple Silicon M line.
Great video Celso, sounds like the A64FX chip could make for a great games console processor too??
When do you think we will see memory on chip on desktop CPU? Zen 4? Would this be more like another cache level and we will keep regular DDR system memory as I just can't see 32GB fitting on a CPU die.
By embedding the hbm on the soc, the processor has a direct link to it and can therefore shift data at much faster rates. It eliminates a huge bottleneck by shortening the bridge between the two.
With all of these extra cores, specific tasks can be assigned, and change more dynamically than ever. Think of it as a logic function: the various cores can change form based on whatever task they are doing, and without it bogging down the system like emulation, for example. All computing is algorithmic, this is just a more advanced form of it.
@@redrumtm3435 Sure, I get that, and that is a great feature/asset to have which is one of the reasons I've been super excited about this chip and following it since the mid 2018 but what I am saying is 32GB of HBM per die seems kind of small for data centre work loads so when you have a data set or even single file that is more than 32GB you will have to split it and send it to different dies which will surely be much slower than have the whole of the data sat in normal system memory where any free CPU can work on the data?
@@Speak_Out_and_Remove_All_Doubt The entire system works so efficiently that data can be transferred much faster. It can achieve much more, but with a lower buffer. The cores are designed to work as one, and vary when and where necessary to suit a particular task.
Basically, the entire thing is the beginning of ARM's transition into a hybridised cloud system that works across all devices. This is how we will cheat Moore's law, and continue to push the envelope so to speak.
@@redrumtm3435 I know Coreteks is a firm believer that ARM is coming for x86, and I agree it will take over certain areas, but I think the PC space is so heavily entrenched in x86 I really can't see it happening but it's great that it is happening on the server side if its faster and using less energy. Coreteks also loves RISC V, i'm not sure which is has the better chance of challenging x86's dominance.
The quality of production and quality content are next level. Always worth the wait. Remember guys quality takes time.
So that is where Arnold Schwarzenegger's Terminator got (or will be getting) its CPU from.
Great video as always! ;)
Informative af
This advanced Fujitsu's A64FX chip variation will be in a Nintendo Switch revision in the future as a complement to the ARM's CPU and Nvidia's GPU
Where can I read about that?
@8:53 - 3TFlops of peak bandwidth?
Floating Point Operations x Bandwidth?
Wouldn't it be 3TB/s of Bandwidth ou 3TFlops of Throughput?
Will the amd chiplets always be so far apart from the IO die (any benefit from stacking etc).
Finally ! My favourite UA-camr coreteks uploaded a video. Love your content man been watching you since the age of 15 in 2019 till now
JustVictor 17 hehhe nice man
JustVictor 17 this technology and semiconductor field is the only place were we all can be together without any bullshit politics and drama of this cruel world.
Just an minor correction: The ring bus was used by Intel for Haswell and Broadwell. From Skylake onward, they are using a mesh interconnect.
Desktop Skylake (and family) uses a ring bus too. The high core count chips use the mesh interconnect.
A great video bro. I am a novice, I am into processors , but really confused in risc and cisc , and how they work??
congrats for your 100k subs!
@coreteks Would love to see a video on the topics from this video as relates the nVidia ARM acquisition.
The end sounds like Cygnus X - Positron but a bit different. Has that anything to do with the presumed change in computing you laid out in this video? If so, that is a masterful match!
Consumer processors will probably use HBM as sort of an L4 cache, or a base memory with a tiering system, and then still have traditional memory channels, though maybe less channels
Damn great video dude
Well, this is Absolutely Amazing.. Thank You Very Much for Sharing..
Greetings from México... !!!
I wonder if Coreteks has any more material for a follow up video. For example, how does this architecture compare to Xeon Phi (Knights Landing) - and how do these differences matter?
The future with ARM processors looks great with this one.
Interesting that Nintendo has an indirect connection to this too. One could imagine their NSO servers running on top of an A64FX processor, maybe a future console? 🤔
Just got here. After watching this it's an instant sub. I can't wait for more.
Great ep worth sharing, thank you!👏👍
A64FX is truly something very special (GO ARM)!
gratzz for 100k...
I didn't understand a thing in this video but I am curious to learn..where to start ?
Blew my mind, as every time.
another great video!
OK, so forgive my ignorance please, but my i7-8700k is maybe 4cm x 4cm x 50mm with just my water cooler head attached to it, and my 1080ti is a whacking great chunk of....stuff.....maybe 100x the volume. Can someone explain to me how you are going to fit a 1080ti into a 8700k?
Why having both the cloud and the edge devices run on the same ISA make it faster and less translation layer?
I'm intensely curious how it handles multimedia workloads. (My bias is towards things like digital music production, where the overall description of what this chip is and does would be ideal)
11:39 No, not all the other memory types did commoditize eventually. I can think of two things that Intel bet on, that flopped: bubble memory, and RAMBUS.
@Coreteks
Did you hear about the new CPU-based AI/neural net "SLIDE" software that runs faster on Xeons than tensor does on Volta?
I didn't think it was humanly possible for your voice to get any lower... You proved me wrong :)
I used to live next to the 京コンピューター Kei Supercomputer in Kobe. Very cool to see these new advancements. 👍🏻
I'd love that ARM CPU in my smartphone...
Not all Arm processors are designed to go in phones. This one would draw way too much power to be usable.
For example the i.MX chip in the Librem 5 and the Allwinner chip in the Pinephone. Both of them were not designed for phones but are being used anyway for their open nature.
@@deoxal7947 I know that dude ... but a man can dream ... The power of the sun in the palm of my hand.
@@deoxal7947 Dude, I want that chip in my wrist band.
I have to wonder how my transistor system I am working on, could impact things using this all-in-one aspect, with memory and more elastic PUs (processor units), I know the Commodore's Amiga 2000 was able to operate audio video and general processing on every processor in the system, which is probably why it was able to match performance of Intel systems of a factor of 5 x the speed, (like a 28.8mhz amiga vs a 150mhz PC) and the transistors I am developing are not binary but quaternary and bipolar, ie, programmable to 3 states in both NPN and PNP status, though what I have in mind has a static memory allowing pulling of power to leave the states behind, also there is no off position, but rather a neutral (0 state meaning it has neither a positive resistance on entry nor a negative resistance on entry, so it just becomes a very low level resistor, or just a conductor, depending on the materials used to deploy the matrix in.) Really can not wait to see what else they pull out of this network of chips in their cloud super computers, might be time to start bumping up the encryption of crypto currencies, or satoshi's canary in the mine one million bitcoin address might be gone before we know it XD
Great video :)
The shape of things to come ...
interesting future ahead,weird its been so silent i just stumbled on this video,saw another video about 80 core arm cpus,the power saving alone is big.
YES YOURE BACK
Cool, thanks.
A certain amount of lust for that dual socket water cooled board with the dual a64fx chips good video and thanks
Correct me if I am wrong because I haven't done low level programming since university.
Doesn't ARM have a totally different instruction set than the x86 platforms (actual binary code and with no equivalent commands, not just in the assembler).
"It runs windows" might be misleading, it runs windows and maybe some apps reassembled for ARM but I'd think that a standard x86 program would run terribly.
So the fact that X runs faster on an ARM chip rather than a Xeon may be just down to the program.
Have I missed some OS tech that allows ARM to accept x86 programs?
Well, what were the APU ranges?