if a processor can snoop w write miss from another processor waht is the utility of the invalidation signal, we can just make it automaticly invalidate a cache line whenever it snoops a write miss from another processor
Is the read hit only if the block was present the the cache of the core attempting to read? or is it a hit so long as any core has it in the shared state?
I don't know what are you asking by 'read hit' but assuming you mean cache hit, data must be in that processor's cache. If not then that processor demands it from the bus and makes it clear that it intends to modifi it so that the bus can invalidate other processor's cache data and supply the data to modifying processor's cache
Dr. Juurlink, What is the need for writing back the block to memory in case block is in M state and Write Miss is detected? I get that you have to go to I state, but why do you need to writeback the data to memory.
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if a processor can snoop w write miss from another processor waht is the utility of the invalidation signal, we can just make it automaticly invalidate a cache line whenever it snoops a write miss from another processor
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Is the read hit only if the block was present the the cache of the core attempting to read? or is it a hit so long as any core has it in the shared state?
I don't know what are you asking by 'read hit' but assuming you mean cache hit, data must be in that processor's cache. If not then that processor demands it from the bus and makes it clear that it intends to modifi it so that the bus can invalidate other processor's cache data and supply the data to modifying processor's cache
Dr. Juurlink, What is the need for writing back the block to memory in case block is in M state and Write Miss is detected? I get that you have to go to I state, but why do you need to writeback the data to memory.