CXL - A PCIe based solution for interconnect | CXL Verification IP | Truechip's VIP

Truechip's CXL Verification IP provides an effective & efficient way to verify the components interfacing with CXL interface of an IP or SoC.
Truechip's CXL VIP is fully compliant with latest CXL specifications. This VIP is a light weight with an easy plug-and-play interface so that there is no hit on the design cycle time.
Compliant with the CXL 1.1 specification
Verification IP configurable as CXL Host and Device when operating in Flex Bus mode and as PCI Express Root Complex and Device Endpoint when operating in PCIe mode.
Support for all three CXL protocols i.e., CXL.io, CXL.cache, CXL.mem and device types to meet specific application requirements with user configurable memory size for both CXL Host and Device.
Support for CXL Downstream and CXL Upstream Port registers (located at RCRB and MEMBAR0)
Support for 32.0 GT/s Data Rate with backward compatibility
Support for Alternate Protocol Negotiation for CXL Mode
Support Pipe Specification 5.1 with both Low Pin Count and Serdes Architecture
Support for ARB/MUX for CXL ALMP transmission and reception to control virtual link state machine and power state transition requests
Support for CXL ACK forcing and Link Layer Credit exchange mechanism
Support Arbitration among the CXL.IO,CXL.cache and CXL.mem packets with Interleaving of traffic between different CXL protocols
Support for randomization and user controllability in flit packing