FPGA #12 - Verilog Always Pt. I (Combinational Circuits)

Using the Verilog always construct to define combinational circuits.
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#verilog

[@axelanderson2030]

Looks like I'm in for a ride! I am very honoured as a young person to have such an experienced individual talk about verilog!

[@JohnsBasement]

Tis I that am honored with such praise!

[@jamesross3939]

Well done and very informative!

[@JohnsBasement]

Thanks!

[@captaindunsell8568]

In the 80s at Andor Systems in Cupertino… Dr. Amdahl’s last mainframe venture … we created, in pascal, compile code simulation. We wrote the entire mainframe in pascal, each subroutine was a chip, that after all the simulation, we wrote our own silicon compiler that used the same source code that was used with the simulation. The verification process was output from the simulation of the pins of the chip at each clock cycle .
This process allowed us to got into production with REV 1 chips… at that time we used 256k gate arrays from NEC…

[@captaindunsell8568]

My chief engineer works for Cadence as their senior field application engineer… aka super customer support

[@JohnsBasement]

Holy cow!!! Now that is some simulation!!!

[@pentachronic]

I have a full top level bench with back annotated RTL simulation with models running on a chip with 1M gates. Works well. Verilog + System Verilog.