Current sources, biasing

[@shubhamroy036]

Attention Please :
At 25:25, I think Sir has made a mistake. The lower two PMOS in the copy circuit (in red) should be NMOS as we can see the Gate and Source are shorted which means the device is in cutoff mode(Vgs = 0), which should not be the case. It should have been in saturation. To do so lower two MOS should be NMOS instead of P.

[@anwesh07]

no, he is correct bcoz in small signal it gate will be ground which we want and in dc analysis capacitor will work as open circuit hence we will get voltage.......

[@shubhamroy036]

In DC analysis ,Vgs of lower two right p mosfets are 0. It is same for AC analysis. Vgs is 0 in all cases. Therefore the lower two MOSFETs act as an open circuit. Hence the circuit won't work at all. Anwesh you can simulate this circuit in Ltspice for a better clarification.

[@anwesh07]

@@shubhamroy036 ya ya got it..... it should be nmos👍✌️.. I didn't notice that..

[@anwesh07]

@@shubhamroy036 bro have u done week 5 assignment (specifically question no. 9)....if yes can u share it with me in Facebook or Instagram..... please...

[@shubhamroy036]

@@anwesh07 Bro I have only followed the youtube videos.

[@maansterminator]

28:14 differential amplifiers topic

[@abinessg6895]

for 4I why is the drain voltage at nmos 2vgst +vt rather than just 2vgst (03:27)

[@abhishek36870]

Because gate voltage has to be 2VSGT +VT and gate and drain are connected together

[@abhishek36870]

When current is I, gate to source voltage is vgst + vt. Here current is 4I so vgst changes to 2vgst. Hence gate to source voltage becomes 2vgst + vt

[@AdityaSingh-pq1fj]

let there be peace 😂

[@nishant1877]

PM Modi got the idea of GST after going through your lectures

[@serendipitous5497]

❤️