Interconnect Modeling (Part 1)

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  • Опубліковано 20 вер 2024

КОМЕНТАРІ • 10

  • @vamseemohanmallela6105
    @vamseemohanmallela6105 4 роки тому +1

    Generally pitch is from the middle of the wire to the middle of the adjacent wire, but we get the idea. Thank You!

  • @chaturbhujrajendran4995
    @chaturbhujrajendran4995 5 років тому +2

    The schematic of the inverter here is wrong. The source of Pmos has to be connected to Vdd. So, the drain of the Pmos and the drain of the Nmos are shorted together from where the output is taken.

  • @debarunsaha8485
    @debarunsaha8485 5 років тому +1

    Sir,Drain of pmos and drain of nmos should be connected at the output.

    • @nitinsonker8429
      @nitinsonker8429 4 роки тому

      yes there is some mistake on that rather things are ok

  • @vayalpadunirupa1697
    @vayalpadunirupa1697 Рік тому

    Why we won't consider inductor in net delay

    • @telugujoshi
      @telugujoshi Рік тому

      It is a second (or even third) order effect. Sometime in the near future, inductors - self and mutual - need to be taken into account.

  • @kranthikumar9998
    @kranthikumar9998 6 років тому +2

    Sir,
    How we will get these ppt's?

    • @anandmaurya4045
      @anandmaurya4045 4 роки тому +1

      www.ifte.de/books/eda/
      Download all slides and reference book from here.