It would be nice if the timeline of this dialogue was indexed, 77 minutes is hard to handle (esp. for a UA-cam audience) ... 00: 00 : mainly INMOS, Occam, Verilog, VHDL 26:06 : RISC 28:00 : ARM 38:00 : Linux, Windows, WSL 40:00: US vs. UK 41:00 Chip IP 45:00 Computational Storage 46:00 Tools, not changing existing software 48:00 Risc-V + FPGA 52:00 EDA status, AI 58:00 State of chip design, state machines 1:01:00 Next 5 years 1:06:00 Hobbies (hardware fun) 1:09:00 Advice for the young ones 1:11:00 Plumbing 1:13:00 Bleeding edge (when stuff falls off) 1:15:00 Lance
I still think there is mileage in designing chips that we know how to program, rather than trying to design chips that can run all the complete rubbish that people have been writing for decades and calling 'software', and I include the interpreters and compilers in that.
Interesting chat. You can clearly see why the Transputer failed from this talk -- this attitude that doesn't seem to grasp the reality of either large scale software development or modern CPU architecture clearly shows how you'd get a bunch of people making something that isn't cost effective and doesn't work for real software developers. Exhibit A, he's still excited about VLIW after basically all VLIW architectures are EOL...! The idea that modern CPU architectures aren't efficient past 2MB of data is... bonkers. Also the idea that RISC-V isn't interesting, but MIPS is beautiful? I regularly hear RISC-V described as the spiritual successor to MIPS, and despite the name it's most definitely not RISC in the late 80s sense any more than ARM (nee Acorn RISC Machine). So I find some of his ideas interesting but I have a lot of questions about his judgement.
It would be nice if the timeline of this dialogue was indexed, 77 minutes is hard to handle (esp. for a UA-cam audience) ...
00: 00 : mainly INMOS, Occam, Verilog, VHDL
26:06 : RISC
28:00 : ARM
38:00 : Linux, Windows, WSL
40:00: US vs. UK
41:00 Chip IP
45:00 Computational Storage
46:00 Tools, not changing existing software
48:00 Risc-V + FPGA
52:00 EDA status, AI
58:00 State of chip design, state machines
1:01:00 Next 5 years
1:06:00 Hobbies (hardware fun)
1:09:00 Advice for the young ones
1:11:00 Plumbing
1:13:00 Bleeding edge (when stuff falls off)
1:15:00 Lance
Thank you @Marcel - I will index as suggested
Time markers added
Nice Talk. Thanks, Kev.
Had me at T-800
I still think there is mileage in designing chips that we know how to program, rather than trying to design chips that can run all the complete rubbish that people have been writing for decades and calling 'software', and I include the interpreters and compilers in that.
Interesting chat. You can clearly see why the Transputer failed from this talk -- this attitude that doesn't seem to grasp the reality of either large scale software development or modern CPU architecture clearly shows how you'd get a bunch of people making something that isn't cost effective and doesn't work for real software developers. Exhibit A, he's still excited about VLIW after basically all VLIW architectures are EOL...!
The idea that modern CPU architectures aren't efficient past 2MB of data is... bonkers. Also the idea that RISC-V isn't interesting, but MIPS is beautiful? I regularly hear RISC-V described as the spiritual successor to MIPS, and despite the name it's most definitely not RISC in the late 80s sense any more than ARM (nee Acorn RISC Machine).
So I find some of his ideas interesting but I have a lot of questions about his judgement.