Lecture 25 - Main Memory and DRAM Basics - Carnegie Mellon - Computer Architecture 2013 - Onur Mutlu

[@Family-r5u]

We live in best life period where inaccessable resources several decades ago, now easily shared and accessed globally

[@ramanarora1134]

Someone please Prof. Mutlu a Nobel Peace Prize for all the great public service he has been doing.
Thank You Sir, your explanation gave me courage and the requisite knowledge to tackle gem5 and gpgpusim

[@thegreatleo2003]

Main Memory starts at 34:51

[@IsaacBeerelliPullarao]

Hi
Can you tell how latency is effecting on memory read and write..?

[@syntempl2426]

amazing

[@anandmirji831]

DRAM @ 50:23

[@IsaacBeerelliPullarao]

Can you tell how latency is effecting on memory read and write..?

[@IsaacBeerelliPullarao]

Can you tell how latency is effecting on memory read and write..?

[@musicmasti2564]

dear sir , isit possible to make register ecc memory to normal computer memory . by removing extra 3 chip , please reply.. thnx