28:00 start 53:00 send the data to write to the slave 56:00 write the data to the slave 58:24 cleanup state 01:06:18 state machine Verilog 01:09:30 testbench 01:20:00 testbench 01:26:30 testbench
Hi.. Its really helpful..!!! Can you please make video on verilog VPI (Verilog Procedural Interface) and PLI(Programming Language Interface)?? There is no video for this two things in UA-cam..!!!
Would you be able to create an ethernet interface video? I struggled with that over my summer internship and it seems like companies are wanting to see more stuff done through the use of ethernet.
To me the next_state thing is much better at writting satte machines because it clearly separates sequential logic and combinational logic and helps you visualize if you are making errors that might generate inferred latches or not...
I have a little question here! You declared i2c_master_single_byte module which is the toplevel of the project and inside it I saw you use i2c_master_byte_ctrl as byte_controller entity which is from the core that you downloaded from the opencores? So in the final compliation we need to include i2c_master_byte_ctrl.v and i2c_master_bit_ctrl.v file in the same folder right?
Hello sir. I want to do an project where I want to use temperature sensor. I'm not getting where to start and hot to start. It's getting diffuclt for me to even to interface with the "PMOD TMP2". I'm doing it on zedboard zynq7000 series. Please suggest something, how shout I begin. Waiting for your reply
I've spent 5 days trying to code an I2C master core and I'm failing miserably. Worse yet, I can't find a working core to compare against. Every video series ends up in a non-working state by the end of it. Can anyone help?
What do you mean by FPGA engineer? If you are an electrical engineer you should know all this stuff by default and you can have your Expertise in any one of them, FPGA, Analog, Digital and VLSI!
28:00 start
53:00 send the data to write to the slave
56:00 write the data to the slave
58:24 cleanup state
01:06:18 state machine Verilog
01:09:30 testbench
01:20:00 testbench
01:26:30 testbench
taught me a lot thanks. State machine style looks cool and nice and simple - good demonstration.
Good information, thanks! Have you considered sharing the actual i2c low level implementation as well?
good job, learning both Verilog and practicing i2c
Keep up live coding with more complex designs. Thx
Bought your board, love your videos, how about floating point and neural networks?
The first bug: You are not receiving the ACK after the address write. You looked at this several times and compared it to the spec and didn't see it.
: cool hack this one . Loved whatever u taught russel
Please make similar video for SPI protocol
Hi..
Its really helpful..!!! Can you please make video on verilog VPI (Verilog Procedural Interface) and PLI(Programming Language Interface)?? There is no video for this two things in UA-cam..!!!
Would you be able to create an ethernet interface video? I struggled with that over my summer internship and it seems like companies are wanting to see more stuff done through the use of ethernet.
To me the next_state thing is much better at writting satte machines because it clearly separates sequential logic and combinational logic and helps you visualize if you are making errors that might generate inferred latches or not...
A combinational process could generate an inferred latch. A clocked process never will.
Also ew.
@@Nandland good to see you are still active. love your channel and website. one day I hope to get a job with fpga and know as much as you.
I have a little question here!
You declared i2c_master_single_byte module which is the toplevel of the project and inside it I saw you use i2c_master_byte_ctrl as byte_controller entity which is from the core that you downloaded from the opencores? So in the final compliation we need to include i2c_master_byte_ctrl.v and i2c_master_bit_ctrl.v file in the same folder right?
Is there a possibility that I can take some expert courses from you? If I'm stuck in a project. I can pay for it.
Did you just use the testbench from the code downloaded from opencores and modified? Slave model needed to be included to test?
Nice
Good information,thanks,can u pls share the verilog code of i2c
Hello sir. I want to do an project where I want to use temperature sensor. I'm not getting where to start and hot to start. It's getting diffuclt for me to even to interface with the "PMOD TMP2". I'm doing it on zedboard zynq7000 series. Please suggest something, how shout I begin. Waiting for your reply
I've spent 5 days trying to code an I2C master core and I'm failing miserably. Worse yet, I can't find a working core to compare against. Every video series ends up in a non-working state by the end of it. Can anyone help?
thx for your tutorial
are the files you created available for download?
I want to learn verilog ,i have gone through your website ,is that enough? what should i do plz guide me
Dear Mr. Russell, could you please upload your verilog code and testbench verilog code on your nandland Github? Thanks in advance.
hi can you help me out with the constraint file for your light sensor on github
Anyone know why he stopped uploading?
May be lack of support dunno? I bought his go board and it arrived quickly but he doesn't seem to acknowledge messages etc.
Hello, I am looking for your name, I wanna reference you to my school work
hi, could programming I2C continue?
Please keep the screen in white background
Start 7:44
Are FPGA Engineers need to Knows VLSI and Analog stuffs?
anyone reply plse
@@francis.joseph add a like 👍
What do you mean by FPGA engineer? If you are an electrical engineer you should know all this stuff by default and you can have your Expertise in any one of them, FPGA, Analog, Digital and VLSI!
Yes we need to know
could you please provide test bench for it
Hello sir
Can inform us before live streaming......?
We can also join this...
Can you make a video of making rock-paper-scissors game using verilog ?