Capacitor Impedance in a PDN: Derivation

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  • Опубліковано 31 тра 2024
  • What mathematics influence a PDN impedance spectrum's shape? Tech Consultant Zach Peterson explores which circuit parameters dominate the shape of the PDN impedance spectrum, as well as derivation in this power integrity video.
    0:00 Intro
    0:39 Where the Shape Comes From
    3:41 Equivalent Circuits
    5:22 Capacitor Impedance
    8:28 Critical Points
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  • Наука та технологія

КОМЕНТАРІ • 5

  • @mostafanfs
    @mostafanfs Рік тому +2

    Hey Zach!

  • @mohannadasar6126
    @mohannadasar6126 Рік тому

    Hi Zach, I remember in "Controlled ESR Capacitors" video that increasing ESR of Capacitor of fres=f1 flattens the curve between Z at fres and the peak point, same for the other capacitor, meaning increasing ESR of both capacitors can give a flat response which reduces the supply voltage oscillation in the time domain. I have a question here, doesn't it make no sense to increase ESR of a capacitor for better performance? or since you're talking about "off-chip" capacitors then it's different, meaning, on-chip capacitors implemented in each block in the SoC could require minimum ESR for other reasons? and off-chip could require high ESR for the flat response? could you explain the difference between the two types of capacitors? off-chip capacitors and on-chip for each SoC block modeled as Cdie & ESR?

    • @Zachariah-Peterson
      @Zachariah-Peterson Рік тому +2

      In that question it was about using a controlled ESR capacitor in a PDN, but that is not really their intended usage. Technically you could use them, but you are correct that it does not make sense to increase resistance if you want to get to a lower PDN impedance. If you used controlled ESR capacitors with higher ESR value to get to a lower PDN impedance then you might need to use a lot of those controlled ESR capacitors in parallel to get the total PDN impedance below target.
      In terms of on-chip, I will admit I have not looked into the controlled ESR aspect of those chip capacitors because I do not do IC design. I will say that those chips have higher capacitance density AND higher ESR so I think the response at high frequencies would naturally be flatter but I would have to look at data to be sure. There will also be differences between the different types of SoC capacitors (MIM, MOS, MOM, etc.)

  • @cvillafane4694
    @cvillafane4694 Рік тому +1

    Hi Zach, in 5:54 equation there is no C.

    • @Zachariah-Peterson
      @Zachariah-Peterson Рік тому +2

      That's because it's lumped into the natural frequency (omega-0).