MOCK | INTERVIEW | VERILOG | PART-2

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  • Опубліковано 31 жов 2024

КОМЕНТАРІ • 6

  • @atharvapotdar5560
    @atharvapotdar5560 4 роки тому +3

    I am a 3rd year VLSI aspirant and Iam learning a lot through these informative and doubt solving sessions. Waiting for more upcoming videos 👍

    • @SemiDesign
      @SemiDesign  4 роки тому +1

      atharva potdar we are here to help !

    • @SemiDesign
      @SemiDesign  4 роки тому +2

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  • @Golukumar-vj6kk
    @Golukumar-vj6kk Рік тому +1

    💥💥💥💥

  • @RahulKumar-oz2mc
    @RahulKumar-oz2mc Рік тому

    at time, 6:34 , inside begin end non blocking used on same signal, is it going to be sequential execution because of begin end??

  • @RahulKumar-oz2mc
    @RahulKumar-oz2mc Рік тому

    at 37:39 , which group are you talking about?