Low Power VLSI Design
Вставка
- Опубліковано 15 вер 2024
- To access the translated content:
1. The translated content of this course is available in regional languages. For details please visit nptel.ac.in/tr...
The video course content can be accessed in the form of regional language text transcripts, books which can be accessed under downloads of each course, subtitles in the video and Video Text Track below the video.
Your feedback is highly appreciated. Kindly fill this form forms.gle/XFZh...
2. Regional language subtitles available for this course
To watch the subtitles in regional languages:
1. Click on the lecture under Course Details.
2. Play the video.
3. Now click on the Settings icon and a list of features will display
4. From that select the option Subtitles/CC.
5. Now select the Language from the available languages to read the subtitle in the regional language.
useful in understaning low power techniques and issues
all NPTEL videos are good
wonderful understanding for the beginners to understand the concept
Its very informative and useful for beginners
What textbook do you recommend? Thanks a lot for the lecture!
30:15 wouldn't the spike in current only correspond to the charging of the capacitor (not the discharging)? because the discharging of the capacitor is current flowing from the positive node of the cap to ground not from the Vdd rail?
As discussed in the inverter scenario, when input changes from high(1) to low (0), ideally the current through the NMOS should be zero (OFF) and the current through the PMOS should be equivalent to Vdd(ON). But in real time scenario, the current through the the PMOS will be a spike (referred as Isw - switching current)(used for charging the capacitance) but the short circuit current comes into play when the same switching current also flows through the NMOS for a short duration (referred as Isc - short circuit current).
Nice one
I don't know what is the difference between switching frequency and a normal frequency. If a signal is random, how do I know exactly the switching frequency of that signal. And why activity factor of clock is 1. Can you prove it by using formula ? Thanks
Normal frequency : Maximum frequency of operation
Usually, in a design, only the clock will toggle every time. The data will not toggle every clock.
Example: Assume the clock toggles 100 times in a second. Clock frequency = 100Hz.
Assume the data toggles 50 times in a second.
Then we say that, activity factor α = 50% => 0.5
This implies that, data switches once, for every two clock switch.
Hence, the data switches at 50Hz (we do not use frequency/Hz with data generally)
We do not calculate power for random signals. We have to always, assume the probability of switching.
We can calculate best case power (α = 0, no switching), typical case power (α = 0.5, 50% switching) and worst case power (α = 1, 100% switching). In the case of chips, we can calculate best case, typical case and worst case power. But, this way of calculating power, will not give us the correct/real-world power consumed by a chip. For finding real power, we have to run simulations based on real-life usage and imitate the real toggle of each and every node in the chip. We have to provide the simulation waveform to the power calculation tool (there are other inputs as well) and we get the power numbers. This method is required, as we cannot manually find the switching frequency for millions/billions of transistors in a chip.
In a real chip, the transistor's dynamic/short ckt/static power is one of the component of total power. The individual wires, connecting the transistors and other components will also consume power.
good
This is lecture 58.
Please put the lecture number in the video text.
search vlsi physical design nptel on UA-cam you will see whole playlist
What textbook do you recommend? Thanks a lot for the lecture!