These are pre-defined terms in the language and their description was inherited in the language itself. Thank you for watching our video. Support us by subscribing and hang on for more useful updates. Thank you.
No Mr. Praveen... It is component declaration part where we just declare the inputs with some formal names. These formal names are used just for identifying the count of inputs and outputs.... But in the component instantiation part, we shouldn't use the same names because they are actuals.... Hope your doubt will be cleared. If not, feel free to message me again. I'll try to solve your doubt in another possible ways. Thank You
Hello Mr. Aditya, thanks for visiting our channel and watching this video. The question is about how logical operations like xor & and are understandable by the software? Those are keywords whose operations were defined during the development of language following IEEE Standards. Similar to keywords like entity, architecture, begin, end, port, component, signal etc., that gets displayed in blue color in the program editor.
Here v have not assigned what operation the xor and 'and' should perform...u hve answred that it is a keyword but v have givn different names like exor and andgate den how is it possible?
Hi Remya, we need not define everything from scratch because the language already had them in its definition. Coming to the terms exor and Andgate, they had nothing to do with the actual logical operation. Component names are for identifying the respective components and have no connection with the actual logical operation performed by those components. If you want, you can also name those components with names of your favorite heroes say "component Rajnikanth" or component "Tom cruise" provided if you can recognize or recall what logic operations were assigned to these names. I hope you got an idea of how the names work. Do contact us for further clarification and also don't forget to subscribe to our channel if you like our video and doubt clarification. Thank you Remya.
@@SkilltroniksTechnologies So the structural logic is written after the dataflow logic? because we defined S and C as output of 'and' and 'xor' respectively in Dataflow logic and not in structural one.
@@nimitjain5553 Hello Mr.Nimit, You need not necessarily write dataflow first and then structural. You can do vice versa also. But one thing you have to remember, you need to make every program ready before compiling. Let us say, you've to shift to a new place from your current location. While loading the items, it doesn't matter if you load sitting room items first and bedroom items next. Order can be anything. Still if your doubt persists, text us. We are always happy to assist you. Thanks for watching our video. Please subscribe if you've not yet done yet and also suggest to your friends. Thank you.
XOR and AND are VHDL keywords inthe library named IEEE. When a programmer write a program and compile it, these are also available in the VHDL environment similar to XOR, AND etc...
Such a wonderful explanation........ Thanks a lot sir
You're most welcome Nandini. Do subscribe for more videos.
Really nice video sirji....
Super explanation sir ....I want more videos from you sir...
Thank u Nandini. Do subscribe for more updates.
Sure, you can find them soon.
I subscribed when I saw your first video
@@mittapallinandini9854 Thank you. Which college do u belong to?
Siddhartha educational academy group of institutions
Love u sir... Very helpfull video in this corona Sem exams
Thank you Yeswant for your response. Share with your friends too. More videos are about to come soon. Thank you.
@@SkilltroniksTechnologies are u trainer
@@yeswantyadav3277 Yes. In which college r u studying?
@@SkilltroniksTechnologies i am from lendi clg sir..
Yes,really nice videos....
Very good work. Thank you very much
thanks s lot great work
Yes, really nice video...
We did not define the logic xor and and anywhere...so how's does this work ??
These are pre-defined terms in the language and their description was inherited in the language itself. Thank you for watching our video. Support us by subscribing and hang on for more useful updates. Thank you.
Bro it's a keyword 🙏
@@bharathhl6935 nvm bro I've graduated now xD
@@wills2618 lol 😂😂 😆😆😆😆😆
Anyways xD sorry
XOR and AND are predefined components available in the library named IEEE....
using x,y,z in the component part of both the gates wont give error??
No Mr. Praveen... It is component declaration part where we just declare the inputs with some formal names. These formal names are used just for identifying the count of inputs and outputs.... But in the component instantiation part, we shouldn't use the same names because they are actuals.... Hope your doubt will be cleared. If not, feel free to message me again. I'll try to solve your doubt in another possible ways. Thank You
Vhdl description for 16:1 mux using 4:1 mux
Hello PSK, we will update the video soon. Do subscribe and hang on for more updates. Thank you.
Keep making video sir
how this program performs 'xor ' and 'and' cause there no information regarding a'b+b'a(for xor gate) and a.b (for and gate)
Hello Mr. Aditya, thanks for visiting our channel and watching this video. The question is about how logical operations like xor & and are understandable by the software? Those are keywords whose operations were defined during the development of language following IEEE Standards. Similar to keywords like entity, architecture, begin, end, port, component, signal etc., that gets displayed in blue color in the program editor.
XOR, AND, OR etc are keywords in VHDL. These are available in the library named IEEE...
Sir
HDL code Anna VHDL code Anna same ha.?
VHDL is a type of HDL
Here v have not assigned what operation the xor and 'and' should perform...u hve answred that it is a keyword but v have givn different names like exor and andgate den how is it possible?
Hi Remya, we need not define everything from scratch because the language already had them in its definition. Coming to the terms exor and Andgate, they had nothing to do with the actual logical operation. Component names are for identifying the respective components and have no connection with the actual logical operation performed by those components. If you want, you can also name those components with names of your favorite heroes say
"component Rajnikanth" or component "Tom cruise" provided if you can recognize or recall what logic operations were assigned to these names. I hope you got an idea of how the names work. Do contact us for further clarification and also don't forget to subscribe to our channel if you like our video and doubt clarification. Thank you Remya.
@@SkilltroniksTechnologies So the structural logic is written after the dataflow logic? because we defined S and C as output of 'and' and 'xor' respectively in Dataflow logic and not in structural one.
@@nimitjain5553 Hello Mr.Nimit, You need not necessarily write dataflow first and then structural. You can do vice versa also. But one thing you have to remember, you need to make every program ready before compiling. Let us say, you've to shift to a new place from your current location. While loading the items, it doesn't matter if you load sitting room items first and bedroom items next. Order can be anything. Still if your doubt persists, text us. We are always happy to assist you. Thanks for watching our video. Please subscribe if you've not yet done yet and also suggest to your friends. Thank you.
XOR and AND are VHDL keywords inthe library named IEEE. When a programmer write a program and compile it, these are also available in the VHDL environment similar to XOR, AND etc...
kindly sir i want the RS 232 receiver code of vhdl kindly also make a video on them
Are you studying? If so furnish your requirements with your details..Let's look into it. Thanks for contacting.
TYSM😄
Always welcome
Thanks sir;
Most welcome
Thank you so much sir 😊
You're always welcome.
Yes, really super class....
Kindly upload more videos on vhdl.
Sure Apoorv, we are already working on it and will get back soon. Thank you for watching our video.