Multicore Memory Caching Issues - Cache Coherency
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- Опубліковано 11 вер 2024
- David Henty (EPCC)
PRACE Summer School 21-23 June 2012 - Summer School on Code Optimisation for Multi-Core and Intel MIC Architectures at the Swiss National Supercomputing Centre in Lugano, Switzerland. - Наука та технологія
So well explained, and the diagrams are awesome. If only all the Operating Systems tutorials on youtube could be this good.
This is exceptionally well explained, particularly because it's such a complex topic.
Great presentation. thank you.
Very instructive! Thanks a lot.
Great piece of work ..
Thank you
At 24:05, the author said "declare a little array and sub sum of two with two values and thread one update the first part of the array and the thread two updated second part." and I am wondering what does it mean. Don't we need two sub sums for the first and half part of the original array? What does it mean by having little array?
You have the following big array "int bigArray[10000]". Thread1 sums up elements 0~4999 and Thread2 sums up elements 5000~9999. The variable used to store the summation is a single array "int littleArray[2]", where Thread1 writes to littleArray[0] and Thread2 writes to littleArray[1].
In the process of the summation, Thread1 loops through the first 5000 elements of bigArray and increments the value of littleArray[0] by each element it sees. Thread2 applies this as well for the last 5000 elements while writing to littleArray[1]. From the shared memory's perspective, the concurrent writing to littleArray causes the false sharing.
nice :D