VHDL Lecture 2 Understanding Entity, Bit, Std logic and data modes

[@shubhadabeldar6747]

Thank you sir for such great explanation of vhdl.

[@jaimilpatel2823]

Part 1 and part 2 of videos both were helpful! Thankyou :D

[@gopalpatil6551]

You r really a very good Teacher....Thanks 4 making such vdos.

[@nfak105]

amazing explanation sir

[@adityakadali]

thank you sir. very good explanation

[@vaibhavkalyankar8650]

Very nice explanationThanks sir

[@zardouayassir7359]

Very good explained , thankyou

[@kapilm5247]

thanks man... very well explained👍

[@landryatamegui5416]

very helpful thanks a lot Doctor

[@samyukthamurugan]

Thank u John it was very helpful

[@windydoo8618]

Thank you Doctor Jonathan Joshi

[@rohitjoshi1258]

very helpful thanks a lot

[@AdarshKumar-tm7pb]

Thank you so much Sir...it helped a lot

[@kaunajbanerjee8526]

STD_LOGIC: Is there a difference between X and W?

[@EDUVANCE]

'X' represents a state where the output of that particular signal couldn't be determined because there were two signals(one HIGH and one LOW) driving that output.
'W' represents a state where the output of that particular signal couldn't be determined because there were two ''weak'' signals(one weak HIGH and one weak LOW) driving that output.

[@josephinlatha3701]

thank you sir

[@sheepman6291]

thank you!!!!