Interesting. So it's not an open source core itself, just an open standard. Any vendor can take it and use it for their proprietary chip. Are SiFive chips fully open source?
I'm looking for standardized PC systems with RISC-V for that the majority of the Linux Distribution can support. I am looking for ATX motherboards or comparable boards with standard boot loaders and other standardized interfaces so that the system can also prevail outside of the nerd corner.
RISC-V linux is at its very early stages, you're looking at 4 more years till you get RISC-V distributions that are stable enough and they would be in beta as well
Funny how most computer breakthroughs come from one or two people doing side projects. Transistor, DOS, Apple I, C, Unix, ARM, Linux, Debian, Risc-V, Rust. Really only LSIC the GUI took big teams and a lot of money.
If there is one important thing, we have experienced in IT history, when it comes to adopt new standards, it is the need for backward compatibility. Remember many examples like the Z80, which only could gain ground because of it's backwards compatibility. Remember game consoles to desktop computers like XBox 360 Emulator on newer game consoles, Rosetta 2, windows Arm x86-64 Emulator. IOMMU is certainly a right step. But RISC-V urgently needs a good backwards compatibility solution to x86-64. Without that even intel failed to replace x86 with itanium.
This is no longer true. Modern software stacks are highly open and highly portable. It is taking a lot of work, but the Android team is working on shipping RISC-V support and they will eventually deliver toolchains that are comparable in experience to existing ones. For many Android apps, rebuilding the APKs for RISC-V will work without needing code changes.
Itanium had combo of at least 3 serious problems, none of which had anything with x86 compatibility. When Itanium was "next big thing" Linux was hobby OS, Unix landscape was fragmented and x86 with Windows had dominant share on desktop. Now there are Linux as established system and GCC/LLVM. And if ARM can be emulated on x86 with QEMU in user mode, something like that is possible for RISC V. But what would be point of that?
You are comparing one Instrcution Set Architecture (RISC-V) to a particular implementation of another Instrcution Set Architecure (Ryzen 7950X as one implementation of x86). This comparison is not working. You probably wanted to ask, if there is a RISC-V based CPU that has better performance than the 7950X. Right now there isnt any. But in the future there probably will be. The reason the Zen4 cores inside the 7950X are faster than any RISC-V core today, is not a limitation of the instruction set. It has more to do with the fact that AMD has decades of experience designing high performance x86 CPUs, while much smaller companies like SiFive only started 2015 with RISC-V from scratch.
HOPEFULLY they all decide to make professional level documentation that shows ALL the relevant information for the ISA in ONE PLACE not scatterbrained throughout one or more documents. As an example FLQ : RV32Q : I-Type | Imm[11:0] | rs1 | 100 | rd | 0000111 | blah blah blah description blah blah blah Showing the mnemonic, the opcode type, the encoding the opcode level and the encoding ALL IN ONE LOCATION not a little piece here, a little bit over there, more info scatterbrained through 2 or 3 other documents... ad infinitum. Look at the Sifive U74 documentation and they start out really well giving all the info in one nice concise blurb... but even here they often show an incorrect number of bits for many different bit field etc. More often than not they dont even state the encoding type (R Type, I Type etc) or even give the encoding at all. NOT HELPFUL!!!!!!!!!!!!!! Risc-V documentation is HORRENDOUS to the level where it is obvious that they cant be bothered to do the job justice. The one thing you can always say about ARM and Intel is that their documentation is SPOT ON. Everything you need to know about a given opcode is stated all together. Sometimes in many different locations. Risc-V documentation is a crap shoot cluster bleep scatterbrained totally unprofessional nightmare.
Looking forward to seeing RISC-V dominance in data centres at the end of this decade.
Interesting. So it's not an open source core itself, just an open standard. Any vendor can take it and use it for their proprietary chip. Are SiFive chips fully open source?
I'm looking for standardized PC systems with RISC-V for that the majority of the Linux Distribution can support.
I am looking for ATX motherboards or comparable boards with standard boot loaders and other standardized interfaces so that the system can also prevail outside of the nerd corner.
I suspect that's years out.
RISC-V linux is at its very early stages, you're looking at 4 more years till you get RISC-V distributions that are stable enough and they would be in beta as well
Nice video, well done, thanks for sharing it with us :)
I cannot wait until someone develops a RISC V server core and we get away from the x86 duopoly that AMD and Intel have right now.
Can you wait 8000 years?
Motorola's 68K was far more popular than most of those proprietary ISA's in the list. So why no mention?
Funny how most computer breakthroughs come from one or two people doing side projects. Transistor, DOS, Apple I, C, Unix, ARM, Linux, Debian, Risc-V, Rust. Really only LSIC the GUI took big teams and a lot of money.
Interesting
No gpu core ???
If there is one important thing, we have experienced in IT history, when it comes to adopt new standards, it is the need for backward compatibility. Remember many examples like the Z80, which only could gain ground because of it's backwards compatibility. Remember game consoles to desktop computers like XBox 360 Emulator on newer game consoles, Rosetta 2, windows Arm x86-64 Emulator.
IOMMU is certainly a right step. But RISC-V urgently needs a good backwards compatibility solution to x86-64. Without that even intel failed to replace x86 with itanium.
This is no longer true. Modern software stacks are highly open and highly portable. It is taking a lot of work, but the Android team is working on shipping RISC-V support and they will eventually deliver toolchains that are comparable in experience to existing ones. For many Android apps, rebuilding the APKs for RISC-V will work without needing code changes.
Itanium had combo of at least 3 serious problems, none of which had anything with x86 compatibility.
When Itanium was "next big thing" Linux was hobby OS, Unix landscape was fragmented and x86 with Windows had dominant share on desktop. Now there are Linux as established system and GCC/LLVM.
And if ARM can be emulated on x86 with QEMU in user mode, something like that is possible for RISC V. But what would be point of that?
Will RISC-V be better than Ryzen 7950X?
Is steel better than Katana?
You are comparing one Instrcution Set Architecture (RISC-V) to a particular implementation of another Instrcution Set Architecure (Ryzen 7950X as one implementation of x86). This comparison is not working. You probably wanted to ask, if there is a RISC-V based CPU that has better performance than the 7950X. Right now there isnt any. But in the future there probably will be. The reason the Zen4 cores inside the 7950X are faster than any RISC-V core today, is not a limitation of the instruction set. It has more to do with the fact that AMD has decades of experience designing high performance x86 CPUs, while much smaller companies like SiFive only started 2015 with RISC-V from scratch.
@NKKKY- one chip manufacturer to keep an eye on is Ventana Micro Systems, they claim their RISC-V processor will be very powerful.
@@Rastor0 thanks
@@realtonaldrum also Tenstorrent with Jim Keller
HOPEFULLY they all decide to make professional level documentation that shows ALL the relevant information for the ISA in ONE PLACE not scatterbrained throughout one or more documents.
As an example
FLQ : RV32Q : I-Type | Imm[11:0] | rs1 | 100 | rd | 0000111 |
blah blah blah description blah blah blah
Showing the mnemonic, the opcode type, the encoding the opcode level and the encoding ALL IN ONE LOCATION not a little piece here, a little bit over there, more info scatterbrained through 2 or 3 other documents... ad infinitum.
Look at the Sifive U74 documentation and they start out really well giving all the info in one nice concise blurb... but even here they often show an incorrect number of bits for many different bit field etc. More often than not they dont even state the encoding type (R Type, I Type etc) or even give the encoding at all. NOT HELPFUL!!!!!!!!!!!!!!
Risc-V documentation is HORRENDOUS to the level where it is obvious that they cant be bothered to do the job justice. The one thing you can always say about ARM and Intel is that their documentation is SPOT ON. Everything you need to know about a given opcode is stated all together. Sometimes in many different locations.
Risc-V documentation is a crap shoot cluster bleep scatterbrained totally unprofessional nightmare.