In looking at the various low cost riscv cpu/SOC it appears the core without floating point is intended to run FreeRTOS to control low level hardware toys like timers, PWM, gpio, and access to the 8051 pic chip in a lot of the soc versions of riscv chips. You then use a mailbox driver between the “big boy” OS like BSD or Linux and FreeRTOS.
I have the feeling there is some weird west/east conflict, the western programmers are hesitant because the hardware is Chinese and the Chinese want a backdoor free CPU (Intel ME, AMD PSP, Apple T2, ARM TrustZone) but don't get the software working.
In looking at the various low cost riscv cpu/SOC it appears the core without floating point is intended to run FreeRTOS to control low level hardware toys like timers, PWM, gpio, and access to the 8051 pic chip in a lot of the soc versions of riscv chips.
You then use a mailbox driver between the “big boy” OS like BSD or Linux and FreeRTOS.
«Of course it runs NetBSD»
But can RISC-V make toast yet?
Next step, bootstrap from bare metal!
I have the feeling there is some weird west/east conflict, the western programmers are hesitant because the hardware is Chinese and the Chinese want a backdoor free CPU (Intel ME, AMD PSP, Apple T2, ARM TrustZone) but don't get the software working.