Thanks for the feedback. I've been thinking of reviving the KiCad series even though it didn't quite get the results I was hoping for. It might depend on how close KiCad 8 seems.
Thanks, just what I was looking for! Google found your video because of the transcript, great that you explain everything in detail so people who are coming in with no kicad vocabulary can still find your videos.
Don't you know you could have made this a 15 minute video with tonnes of waffling and pointless talk while simultaneously skipping over the important parts? I kid I kid, this is perfect. I wanted to use a bus in 7, i read the manual I tried for 20 minutes and I couldn't work it out. This is perfect! to the point, and showing every step you need to do along the way. Thanks so much.
Note: I've used the term "unroll" interchangebly with "unfold." They're the same operation. Due to low viewership, this series will end earlier than planned. 0:00 - Objectives 0:30 - Vector bus 1:17 - Group bus 2:01 - Grouped vectors bus 2:36 - Bus Alias
Thanks for the feedback! I didn't want to end the series before mentioning busses, since they're a bit strange here compared to other programs. I kind of feel the same about differential pairs in the PCB editor.
Talk about doing things the long way around, they couldn't have come up with a more obtuse and confusing way to connect to bus. Diptrace - route bus, connect to bus, add net name, done. KiCAD - well, this.
@@unboxing_tomorrow I'm not even sure about the current state of affairs with KiCAD - its bad, horrible even, for simple projects - sure, anything more than 100 pins and all the ugly becomes visible.
Short, no nonsense, clearly explained, awesome! Is it possible to use buses for "one to many" to avoid ERC warnings? IE: pin RA0 on MCU to pins D+ and PGD on separate components? KICAD decides what it will name the net, I'd like to name it by my MCU pin name (like RA0 and RA1).
Good question! Every net on the bus can be unfolded an unlimited number of times. So for one-to-many situations, I would label the bus first, and then unfold the wire/label as many times as needed. Doing it in this order will avoid net naming conflicts that could cause ERC Warnings. Because labels have priority over KiCad's auto-assigned net names, this is guaranteed to get you the net name you want.
Do you know a way to combine serveral bus aliases in one? I would like to recreate a similar behavior as the harnesses in Altium Designer. What I tried that is possible is "{ Signal1 Signal2 SignalN BUS[0..15] }". But if you have many signals or long net names, this string consumes a lot of space on the schematic. So unfortunately "{ {panel} {SPI} }" or "{ {SPI} Signal1 Signal2 }" is not possible 😥
Wow, wow, wow, wow, just WOW! This is exactly what I have been looking for. Thank you SO FREAKING MUCH. I love you, man.
Thanks for the feedback. I've been thinking of reviving the KiCad series even though it didn't quite get the results I was hoping for. It might depend on how close KiCad 8 seems.
Thanks, just what I was looking for! Google found your video because of the transcript, great that you explain everything in detail so people who are coming in with no kicad vocabulary can still find your videos.
Very concise and immensely useful. Thanks for the video, shame about the low viewership :)
Don't you know you could have made this a 15 minute video with tonnes of waffling and pointless talk while simultaneously skipping over the important parts? I kid I kid, this is perfect. I wanted to use a bus in 7, i read the manual I tried for 20 minutes and I couldn't work it out. This is perfect! to the point, and showing every step you need to do along the way. Thanks so much.
Thank you! I wasn't sure these videos were doing much good.
Note: I've used the term "unroll" interchangebly with "unfold." They're the same operation. Due to low viewership, this series will end earlier than planned.
0:00 - Objectives
0:30 - Vector bus
1:17 - Group bus
2:01 - Grouped vectors bus
2:36 - Bus Alias
Great tutorial! Can you show us how you use busses from a parent to children in a heirarchical design?
Thanks for this video, I've been scratching my head after updating from Kicad 5 to Kicad 7 on this one!
yes, it's different. It still works similarly as in version 6, but they are much much easier to use now!
Thanks for the feedback! I didn't want to end the series before mentioning busses, since they're a bit strange here compared to other programs. I kind of feel the same about differential pairs in the PCB editor.
Talk about doing things the long way around, they couldn't have come up with a more obtuse and confusing way to connect to bus.
Diptrace - route bus, connect to bus, add net name, done.
KiCAD - well, this.
I'm hoping this feature and differential traces have a little more discoverability in the next major release.
@@unboxing_tomorrow I'm not even sure about the current state of affairs with KiCAD - its bad, horrible even, for simple projects - sure, anything more than 100 pins and all the ugly becomes visible.
Short, no nonsense, clearly explained, awesome!
Is it possible to use buses for "one to many" to avoid ERC warnings? IE: pin RA0 on MCU to pins D+ and PGD on separate components?
KICAD decides what it will name the net, I'd like to name it by my MCU pin name (like RA0 and RA1).
Good question! Every net on the bus can be unfolded an unlimited number of times. So for one-to-many situations, I would label the bus first, and then unfold the wire/label as many times as needed.
Doing it in this order will avoid net naming conflicts that could cause ERC Warnings. Because labels have priority over KiCad's auto-assigned net names, this is guaranteed to get you the net name you want.
could you also show example of using this bus with different sheet in hierarchy
Sorry, I don't make videos any more. But for hierarchy, you'll need to unroll all signals until busses also get a hierarchy update.
Thank you! 😍👍
Thanks for the feedback!
Do you know a way to combine serveral bus aliases in one? I would like to recreate a similar behavior as the harnesses in Altium Designer. What I tried that is possible is "{ Signal1 Signal2 SignalN BUS[0..15] }".
But if you have many signals or long net names, this string consumes a lot of space on the schematic. So unfortunately "{ {panel} {SPI} }" or "{ {SPI} Signal1 Signal2 }" is not possible 😥