sta lec18 understanding timing report part 2 | Static Timing Analysis tutorial | VLSI

Поділитися
Вставка
  • Опубліковано 4 лют 2025

КОМЕНТАРІ • 4

  • @vinayakakarthik4259
    @vinayakakarthik4259 Рік тому +2

    Thanks

  • @raveenasaldana3633
    @raveenasaldana3633 3 роки тому

    will primary clock always be zero (Incr) in arrival time . if not what could be the reason?

  • @komatisurendra4751
    @komatisurendra4751 2 роки тому

    How to optimize the path and how to reduce slack value is zero

    • @vinayakakarthik4259
      @vinayakakarthik4259 Рік тому

      There is data opt,you can go for path grouping and retiming ,
      Then reduce the clock period iteratively to get slack zero.