Hi, great video! I just had a doubt: there are other UART projects available online which use a BaudRateGenerator module as well....why is such a module not necessary for this project?
Hi, I tried your code and the loopback works perfectly. But I cannot get the TX to work on it own, I receiver either a wrong character or garbage on the serial terminal. I made sure that settings like baud rate match on both pc and the FPGA board. I load a new byte and hold dv high for 1 cycle. By inspecting the received characters I think it some how drops the first 2 bits of each char, even through the output so correct in a simple test bench I wrote. Great staff by the way keep going.
Transmitter module does not synthesize appropriately. The problem might be my beginner hdl skills. I've tried to write a UART by myself while grabbing ideas and code from this video when I stuck. My "final" version wasn't satisfying so I decided to copy the full code and synthesize it to see the possible difference and the working output. However this module (the transmitter) does not synthesize (Vivado) appropriately, and it only uses 1 LUT and 2 Flip-flops. I've copyed the full code and tried to connect my switches as 8bit data and a button to trigger the transmit (data valid) event. I've also tried to find the error with no luck, however I've tried another UART implementation and it worked accordingly so it must be an internal module logic "error" in your code. (Edit: simulation looks okay, I don't know what is wrong)
I bet anything your outputs are not corrected correctly. The synthesis tools are removing all of your logic because it doesn't think that the outputs are used. Double check your design from the outputs backward.
@@Nandland Thanks for the fast reply! I finally found the root cause. I was trying to use a 9600 baud rate with a 100Mhz clock but the clock counter register was only 8 bit and could never count up that much, so eventually the synthesis figured this out and just left my input out because it was unreachable. Great content, much thanks for the effort!
Sir, i am using the top level module but it isnt simulating on a clock greater than 25MHz. I have a FPGA with 100MHz clock, spartan 6 so i was trying to simulate using that. What can be the possible reason.? Also i devised a frequency divider which is simulating but it isnt working on the board.
Is there the opportunity to send files from fpga to computer? For example I implement in vhdl code to produce hex files where I have some information about the export data. First of all is this synthesizable ? And if it is can I export this file from UART?
Sir, I'm wondering why you don't do the sampling in the middle of the bits as opposed to the receiver (the (CLKS_PER_BIT-1)/2 operation in the Receiver) ? Thank you for the explanation.
On the TX side you SEND bits out, no sampling here. On the receiver you are receiving the transmitted data, so there you need to find the middle of the bit period.
The receiver and transmitter don't use a clock. With a UART you need to oversample the data. When you oversample, you don't really need to worry about crossing clock domains. Just look for the middle of the bits.
@@Nandland Thank you for responding. I came across a problem which mentioned that both Rx & Tx were sourced by the same clock. Won't there be any differences to sampling in such a case?
To help anyone else who runs across this issue: I had to remove the reset logic to get the transmitter to work. For some reason, the reset logic made the synthesizer think the entire transmitter was unused, so it removed it all.
So to initiate an unsolicited transmission from the FPGA we simply assign the data byte (the letter "A" for example) to i_TX_Byte and set i_TX_DV high? I am trying to get the FPGA to send data to the computer without first requesting it (periodically via timer/counter or when I press a button)
Yes, that should work! Just set i_TX_DV high for one clock cycle and the UART_TX takes care of the rest. Gotta ensure your params are set correctly for the baud rate, make sure the computer and the FPGA agree on stop bits, baud rate, parity, and you should be good to go.
how to make changes in UART_TX.v file if I want to give an input (to the transmitter) from the code itself? eg.) I want to give input "ABC12" as input to the transmitter?
Some tutorials show writing FSM logic with next state combination logic. Can you explain why they do this. Doesn't seem like you have that model here for your UART FSM. Thanks Update: Is what you show is considered 1 process and what I am asking is considered 2 process FSM?
+First Last yes I’ve seen that. I think historically this was easier for synthesis tools so lots of “old timers” still use this. I find it really confusing for beginners, so I stick with single process.
Is there a reason for describing the assignment of 'o_TX_Done' and 'o_TX_Active' differently in the VHDL code? I'm I correct in assuming both ways have the same effect at the end of the day... and it's a matter of preference?
They're actually different and serve different purposes. o_TX_Done tells another module that the transmitter is done (so it can accept a new byte). o_TX_Active is continuously high while the transmitter is active. I use that in some half-duplex applications to control a tri-state buffer. The Go Board is full duplex, so no need for o_TX_Active on that board.
What I meant is that you go through the effort of creating a signal `r_TX_Done` which you use to assign to `o_TX_Done` whereas you assign to 'o_TX_Active' directly in the code. Is there a reason for this?
Ah, TX Active is assigned combinationally, were-as TX done is creating a physical register. Said another way, TX Active is outside of a sequential process, TX Done is inside a sequential process. Combinational vs. Sequential logic. If you don't know the difference read this: www.nandland.com/vhdl/tutorials/tutorial-process-part1.html. EDIT: I'm wrong, I was not looking at the right code, see answer below.
Thank you for the replies! I read the article but I still don't understand. TX_Active is assigned inside a process that is sensitive to the clock. Does this not then make it a sequential assignment that generates a flip flop? www.nandland.com/vhdl/tutorials/tutorial-process-part2.html
Thanks for great conitribution
Hi, great video!
I just had a doubt: there are other UART projects available online which use a BaudRateGenerator module as well....why is such a module not necessary for this project?
Can you do a video for a user with parity?
input i_Rst_L, is included on EDA playground but not here.
Can you make video about the axis stream in vhdl 😍. Thanks!!
Hi, I tried your code and the loopback works perfectly. But I cannot get the TX to work on it own, I receiver either a wrong character or garbage on the serial terminal. I made sure that settings like baud rate match on both pc and the FPGA board. I load a new byte and hold dv high for 1 cycle. By inspecting the received characters I think it some how drops the first 2 bits of each char, even through the output so correct in a simple test bench I wrote.
Great staff by the way keep going.
thanks! it really helps a lot !!
are there a chance you can make a SPI and I2C one
Second this
If I am receiving one byte , How can I transmit 2 bytes in return in a similar UART module..? Could you pls send the logic
Transmitter module does not synthesize appropriately.
The problem might be my beginner hdl skills. I've tried to write a UART by myself while grabbing ideas and code from this video when I stuck. My "final" version wasn't satisfying so I decided to copy the full code and synthesize it to see the possible difference and the working output. However this module (the transmitter) does not synthesize (Vivado) appropriately, and it only uses 1 LUT and 2 Flip-flops. I've copyed the full code and tried to connect my switches as 8bit data and a button to trigger the transmit (data valid) event. I've also tried to find the error with no luck, however I've tried another UART implementation and it worked accordingly so it must be an internal module logic "error" in your code. (Edit: simulation looks okay, I don't know what is wrong)
I bet anything your outputs are not corrected correctly. The synthesis tools are removing all of your logic because it doesn't think that the outputs are used. Double check your design from the outputs backward.
@@Nandland Thanks for the fast reply! I finally found the root cause. I was trying to use a 9600 baud rate with a 100Mhz clock but the clock counter register was only 8 bit and could never count up that much, so eventually the synthesis figured this out and just left my input out because it was unreachable.
Great content, much thanks for the effort!
Do people you work with also write many HDL modules with no block diagrams?
This is still the best videos on FPGAs I can find.
Sir, i am using the top level module but it isnt simulating on a clock greater than 25MHz. I have a FPGA with 100MHz clock, spartan 6 so i was trying to simulate using that. What can be the possible reason.? Also i devised a frequency divider which is simulating but it isnt working on the board.
Is there the opportunity to send files from fpga to computer? For example I implement in vhdl code to produce hex files where I have some information about the export data. First of all is this synthesizable ? And if it is can I export this file from UART?
Sir, I'm wondering why you don't do the sampling in the middle of the bits as opposed to the receiver (the (CLKS_PER_BIT-1)/2 operation in the Receiver) ? Thank you for the explanation.
On the TX side you SEND bits out, no sampling here. On the receiver you are receiving the transmitted data, so there you need to find the middle of the bit period.
Is it not necessary to do a cdc, since the receiver and transmitter are in different clk domains?
The receiver and transmitter don't use a clock. With a UART you need to oversample the data. When you oversample, you don't really need to worry about crossing clock domains. Just look for the middle of the bits.
@@Nandland Thank you for responding. I came across a problem which mentioned that both Rx & Tx were sourced by the same clock. Won't there be any differences to sampling in such a case?
To help anyone else who runs across this issue: I had to remove the reset logic to get the transmitter to work. For some reason, the reset logic made the synthesizer think the entire transmitter was unused, so it removed it all.
Thank you
What can be done to make this 32 bit UART instead of 8 bit?
You can only send 8 bit via UART
So to initiate an unsolicited transmission from the FPGA we simply assign the data byte (the letter "A" for example) to i_TX_Byte and set i_TX_DV high? I am trying to get the FPGA to send data to the computer without first requesting it (periodically via timer/counter or when I press a button)
Yes, that should work! Just set i_TX_DV high for one clock cycle and the UART_TX takes care of the rest. Gotta ensure your params are set correctly for the baud rate, make sure the computer and the FPGA agree on stop bits, baud rate, parity, and you should be good to go.
can we implement this code in xilinx software.
if we can do that that plz help me to verify it on xilinx.
Yes you can! Unfortunately I'm unable to help with specific projects.
how to make changes in UART_TX.v file if I want to give an input (to the transmitter) from the code itself? eg.) I want to give input "ABC12" as input to the transmitter?
Some tutorials show writing FSM logic with next state combination logic. Can you explain why they do this. Doesn't seem like you have that model here for your UART FSM. Thanks
Update: Is what you show is considered 1 process and what I am asking is considered 2 process FSM?
+First Last yes I’ve seen that. I think historically this was easier for synthesis tools so lots of “old timers” still use this. I find it really confusing for beginners, so I stick with single process.
nandland I find your way more intuitive. Just wanted to make sure there wasn't any difference in performance. Thanks
@@danviet864 there are differences between assigning in different ways through FSM modelling
Is there a reason for describing the assignment of 'o_TX_Done' and 'o_TX_Active' differently in the VHDL code? I'm I correct in assuming both ways have the same effect at the end of the day... and it's a matter of preference?
They're actually different and serve different purposes. o_TX_Done tells another module that the transmitter is done (so it can accept a new byte). o_TX_Active is continuously high while the transmitter is active. I use that in some half-duplex applications to control a tri-state buffer. The Go Board is full duplex, so no need for o_TX_Active on that board.
What I meant is that you go through the effort of creating a signal `r_TX_Done` which you use to assign to `o_TX_Done` whereas you assign to 'o_TX_Active' directly in the code. Is there a reason for this?
Ah, TX Active is assigned combinationally, were-as TX done is creating a physical register. Said another way, TX Active is outside of a sequential process, TX Done is inside a sequential process. Combinational vs. Sequential logic. If you don't know the difference read this: www.nandland.com/vhdl/tutorials/tutorial-process-part1.html. EDIT: I'm wrong, I was not looking at the right code, see answer below.
Thank you for the replies! I read the article but I still don't understand. TX_Active is assigned inside a process that is sensitive to the clock. Does this not then make it a sequential assignment that generates a flip flop? www.nandland.com/vhdl/tutorials/tutorial-process-part2.html
What code are you looking at?