Hi, to you from Russia :) For me your work is just a find! I'm very grateful to you. For a long time I was looking for the right solution to raise the level and to lower the level. It turned out that you need a special design shown by you. Once again, THANK YOU VERY MUCH! Health to you and long life! Привет вам из России :) Для меня ваша работа просто находка! Я очень вам благодарен. Очень долго искал правильное решение для поднятия уровня и для понижения уровня. Оказалось что необходима специальная конструкция показанная вами. Ещё раз БОЛЬШОЕ СПАСИБО! Здоровья вам и долгих лет жизни!
thanks for the explanation, it really helped me understand the working principle. please is it possible to use this same circuit for 'level shift down', but using switches with the appropriate ratings?
Vcc(3.6) at source of PMOS and 0 at Gate will provide sufficient Vgs (which should be negative for PMOS) to turn on the PMOS. As a result, the PMOS drain gets pulled up to Vcc
You are drawing pmos and saying n channel transistors in last schematic. is that mistake schematic wise. Those should be NMOS so that weak 1 will transferred to lower nmos devices.
Hi, to you from Russia :) For me your work is just a find! I'm very grateful to you. For a long time I was looking for the right solution to raise the level and to lower the level. It turned out that you need a special design shown by you. Once again, THANK YOU VERY MUCH! Health to you and long life!
Привет вам из России :) Для меня ваша работа просто находка! Я очень вам благодарен. Очень долго искал правильное решение для поднятия уровня и для понижения уровня. Оказалось что необходима специальная конструкция показанная вами. Ещё раз БОЛЬШОЕ СПАСИБО! Здоровья вам и долгих лет жизни!
Very nicely explained effortlessly... Thank u very much
really nice explination and helped me to understand well about this level shifter concepts..Thanks eeKnowHow....
Very good video.
nyccccc explaination
Thanks for video....Can u please help me on these
1.How tap cell removes latchup?
2.why latchup increases if distance between tap cell increases?
thanks for the explanation, it really helped me understand the working principle. please is it possible to use this same circuit for 'level shift down', but using switches with the appropriate ratings?
Good explanation
5:48 Why when the gate is grounded the voltage will be pulled up? Thanks!
Vcc(3.6) at source of PMOS and 0 at Gate will provide sufficient Vgs (which should be negative for PMOS) to turn on the PMOS.
As a result, the PMOS drain gets pulled up to Vcc
@@anirudht3232 Thank you for your reply! Understood!
Why Simple inverter can't be used as upshifter? but it can be used as downshifter.
You can use an open drain transistor as a level shifter, but keep in mind that it will invert the signal.
Hi, great tutorial. I would like to learn from you! Could you make more videos about CMOS analog designs? Like LDO/Charge Pump/POR/OPAMPs, etc.
After 5 seconds video gets stuck. Can u provide any other link to play this video
You are drawing pmos and saying n channel transistors in last schematic. is that mistake schematic wise. Those should be NMOS so that weak 1 will transferred to lower nmos devices.
I think it is N-Channel only. If you observe, the bubble is placed differently than a PMOS symbol. Here this bubble denotes Zero Vt device I guess...
Nice explanation