Capacitor Amp-Sec balance explained using LTspice simulation

In this video I have explained the basic principle behind amp-sec balance in a capacitor using LTspice simulations. As per amp-sec balance principle: For a periodic voltage, average current through the capacitor in steady state should be zero .

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I simulated current source connected to capacitor in LTSpice. But, I got an error.
As the theory, capacitor voltage will ramp, but why in LTSpice can't simulate it?