Derivation for Setup and Hold time equations | in Flip Flop | With Numerical example | Part -1

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  • Опубліковано 7 лис 2024

КОМЕНТАРІ • 9

  • @StrifeTheDanceHub2309
    @StrifeTheDanceHub2309 2 роки тому +1

    excellent explanation

    • @TeamVLSI
      @TeamVLSI  2 роки тому

      Glad you liked it!

  • @amitrajdokania
    @amitrajdokania 3 роки тому +2

    In case of Half cycle path, hold equation will be dependent on clock period!

  • @marripatiusharani7146
    @marripatiusharani7146 3 роки тому +1

    Pls upload videos on amba protocols

    • @TeamVLSI
      @TeamVLSI  3 роки тому

      Okay, Wil try to do.

  • @ashutoshchaubey3202
    @ashutoshchaubey3202 Рік тому +1

    Sir whatsapp group link is inactive now... Can u plzz activate it....

    • @TeamVLSI
      @TeamVLSI  Рік тому

      Sure Ashutosh,
      You can join us through following link:
      WhatsApp:
      chat.whatsapp.com/HzCxJjtXgLP9j13R7m5HHq
      Telegram :
      t.me/teamvlsi
      Thanks.

    • @ashutoshchaubey3202
      @ashutoshchaubey3202 Рік тому

      Sir can u make a video on RTL to GDS flow using cadence.... Lots of people are asking for it....