Thank you so much sir. Being a beginner in this area ,your lectures are helping me a lot. To find lectures related to these topics ,that too at free of cost is not at all easy.Thank you so much for your kindness.
Hi. I have a doubt. How LVS (layout versus schematic) will pass though the physical designer adds new cells like buffer, diode etc., and new nets to connect the same in physical design which is different from schematic design?
That is an important question, but the answer is actually kind of simple. The LVS flow that I am explaining here is not comparing the RTL or the post synthesis netlist to the layout, because these two things are not equivalent. As you said, they have additional buffers and whatnot that are added to the design - do not change the functionality - but are undoubtedly electrically different. What this LVS flow is doing is to compare the SIGNOFF netlist with the SIGNOFF layout. These should trivially be the same, since you would generally be producing them from the same tool (e.g., Innovus or Fusion). But they may not be because the implementation tool uses abstracts (.lef files) to be able to run with high enough performance. And sometimes this leads to errors. (note, there probably are many other reasons, but this is kind of the high level primary reason). So we are comparing the design AFTER inserting all the buffers and whatnot. I hope that clarifies it.
@AdiTeman Thank you so much for reply Sir. Just for further clarification, at what stage we are comparing our signoff netlist / layout netlist with RTL netlist/synthesized netlist ( Golden netlist ). Though they are functionally the same, how do we validate it.
Hi. I believe this is elaborated upon during the lecture series - I suggest to watch all the sections and get the full explanation. But, in general, DRC are rules for manufacturing. The fab cannot (or, at least, will not) manufacture polygons that don't meet the DRC requirements. ERC, on the other hand, are more of a sanity check that complements LVS, making sure you don't have shorts or opens in your design and that your bulks are connected.
Thank you so much sir. Being a beginner in this area ,your lectures are helping me a lot. To find lectures related to these topics ,that too at free of cost is not at all easy.Thank you so much for your kindness.
You are most welcome
Thank you so much for this course as well as other tutorials regarding EDA Dr. Teman, you're amazing.
You're very welcome!
Hi Adi Teman, why you took long time to upload new videos..! Please do more videos like this in future. We love your videos from India :)
Thanks. Lots of work lately. Hopefully at some point I will have more time and will make them more frequently :)
Hi. I have a doubt. How LVS (layout versus schematic) will pass though the physical designer adds new cells like buffer, diode etc., and new nets to connect the same in physical design which is different from schematic design?
That is an important question, but the answer is actually kind of simple.
The LVS flow that I am explaining here is not comparing the RTL or the post synthesis netlist to the layout, because these two things are not equivalent. As you said, they have additional buffers and whatnot that are added to the design - do not change the functionality - but are undoubtedly electrically different.
What this LVS flow is doing is to compare the SIGNOFF netlist with the SIGNOFF layout. These should trivially be the same, since you would generally be producing them from the same tool (e.g., Innovus or Fusion). But they may not be because the implementation tool uses abstracts (.lef files) to be able to run with high enough performance. And sometimes this leads to errors. (note, there probably are many other reasons, but this is kind of the high level primary reason).
So we are comparing the design AFTER inserting all the buffers and whatnot.
I hope that clarifies it.
@AdiTeman Thank you so much for reply Sir. Just for further clarification, at what stage we are comparing our signoff netlist / layout netlist with RTL netlist/synthesized netlist ( Golden netlist ). Though they are functionally the same, how do we validate it.
Nice sir 🤗 keep going
Thank you, I will
Difference between Design rule check and Electrical rule check
Hi. I believe this is elaborated upon during the lecture series - I suggest to watch all the sections and get the full explanation. But, in general, DRC are rules for manufacturing. The fab cannot (or, at least, will not) manufacture polygons that don't meet the DRC requirements. ERC, on the other hand, are more of a sanity check that complements LVS, making sure you don't have shorts or opens in your design and that your bulks are connected.
@@AdiTeman thank you ✨